SU1251335A1 - Device for detecting errors - Google Patents

Abstract

The invention can be used in devices for measuring the accuracy of information transmission in digital paths. The purpose of the invention is to improve accuracy. The device contains three adders 1, 2 and 3 modulo two (SMD), comparator 4, four triggers (T) 5, 6, 7 and 8 two counters (C) 9 and 10, the element OR 11 and the Ustontochny shift shift register 12. When information arrives at the input of the device, the C 10 starts counting the clock intervals. After passing 2 clocks at outputs C 10 and T 6, 7 and 8, a logical unit is established and the device begins to function as an error detector. If a failure occurs in the shift register 12, then at the output of the SMD 3 in ts pulses, which, affecting T 6, set a logical zero at its output. From 10 it will start to work and the device will proceed to the successive stages of synchronization of work until the device is automatically resynchronized. The measurement process is interrupted for a short time, equal to the resynchronization time of the device, and then continues. The goal is achieved by the introduction of SMD 3, T 6, 7 and 8 and C 10. 1 Il. Clock Input (LIU 01 co

Description

one

The device relates to a measurement technique, in particular, to devices measuring the accuracy of information transmission in digital paths, and can be used to isolate erroneous symbols from information sequences coming from a digital path to the input of transmission error rate meters.

The purpose of the invention is to improve accuracy.

The drawing shows the electrical circuit of the error detection device.

The device contains the first - the third adders 1-3 modulo two, the comparator 4, the first - the fourth, the triggers 5-8, the first 9 and the second 10 counters, the element OR 11 and the shift register 12.

The device works as follows.

After switching on the device, the synchronization pulse sets the second trigger 6, the second counter 10, as well as the third and fourth triggers 7 and 8 to the initial state, at which the outputs of the counters and the third trigger 7 set the level of "Log. 1, and on the output of the fourth trigger 8, the level of Lo1 O. The signal from the output of the second counter 10, passing through the first trigger 5, sets a logical zero at the second input of the adder 1 modulo two, which is an error corrector. In connection with this, the first modulo 1 adder 1 starts working as an OR element.

In this case, information from the device input enters the inputs of the shift register 12 and the comparator 4, and the second counter 10 starts the counting of clock intervals.

The points of connection of adder 2 modulo two to the shift register 12 in the device for detecting errors in the receiving part of the equipment for checking the communication channel should be the same as in the transmitting part forming the test signal in the form of a pseudo-random sequence (PRS).

Consequently, if there is no error in the input signal, the information at the inputs of the comparator 4 should be the same, and the output of the comparator 4 should be set to the "Log. O (no error).

The first 2 cycles of operation (BI capacity; O-counter 10) the device is synchronized. In this case, the shift register 12 is filled with information, but also the control pulses, if they occur at the output | Impi Rai 4, n the first counter 9, which is the counter ohioil, does not arrive at eleHT OR 11 and further to the second counter K), since the first trigger 5 is closed.

After passing 2 clocks in the circuit, the following changes will occur.

At the outputs of the second counter 10, third and fourth triggers 7 and 8, a logical zero is set. At the same time, firstly, the first sum. Mater 1 modulo two will start working as an EXCLUSIVE OR element, and secondly, the impulses of the error can come through the first trigger 5 and the open element OR 11 to the installation inputs of the second counter 10 and triggers 7 and 8. In the period between 2 and 2 clock cycle, the information recorded in the shift register 12 at the first stage is checked. From the moment the first etam is finished, only faultless information is recorded in the shift register 12, since all the errors are corrected by the first adder 1 modulo two. If, however, at least one erroneous bit of information was recorded in the shift register 12 of the shift register 12, this will cause the error bit through the first trigger 5 and the OR 11 element to go to the installation inputs of the first counter 10 and the trigger 7 and 8 , set them back to their original state, and the device synchronization process starts again, which will continue in the general case until an error-free piece of information is written to the shift register 12 at the first stage.

After passing the clocks at the outputs of the second counter 10 and the triggers 7 and 8, the level Log. 1. The same level will be set at the output of the second trigger 6, prohibiting the further operation of the second counter 10, and the element OR 11 will be closed. From this point on, the device begins to function as an error detector, and the error symbols extracted from the stream of information symbols from the output of comparator 4 through the first trigger 5 arrive at the first counter 9. During normal operation of the device, the information on both inputs of the third adder 3 modulo two matches and therefore pa its output forms a logical zero.

If during the normal operation of the device, a failure occurs in the shift register 12, the output of the third adder 3 but modulo two in TC pulses, which, affecting the installation input of the logical pool of the second trigger 6, sets the logical zero at its output, the second counter starts working 10 and the device again goes to the first stage of work - synchronization, then to the second stage, etc. until the device resynchronizes automatically. In this case, the measurement process will be interrupted for a time of the same time, equal to the device rearranging time, and then it will be continued.

Claims (1)

Invention Formula A device for detecting errors containing a serially connected first modulo two, a shift register, a second modulo two, a comparator, the first trigger and the first counter, the first input of the first modulo two adder being connected to the other input of the comparator , the additional output of the shift register is connected to another input of the second modulo-two adder, characterized in that, in order to increase accuracy, the OR element and the serially connected t are introduced into it the second module modulator, the second trigger, the second counter, the third trigger and the fourth trigger, the output of which is connected to the input For setting the logical unit of the second trigger, the first input of the third modulo-two adder is connected to the output of the first modulo-two adder, the second input is connected to the output of the second modulo-two adder, and the output is the setup input of the device, the clock input of which is the second clock input the counter, the direct output of the first trigger is connected to the second input of the first modulo-two adder, the installation input of the logical unit is connected to the output of the second counter, and the inverse output through the OR element is connected to the info mation input of the second counter, a fourth latch input for setting the logical unit and a logic zero input for setting the third flip-flop, whose output is connected to another input of the OR element.