SU1345322A1 - Device for shaping code sequences - Google Patents

Abstract

The invention can be used in automatic data processing systems. The purpose of the invention is to improve the reliability and expansion of 26 2 the functionality of the device. The device contains a pulse generator 1, a D-flip-flop 2, an AND 3 element, a frequency divider, a delay element 5, a pulse counter 6, a comparison block 7 and address counters 8 and 15. In addition, the device includes memory blocks 9 and 16, the demultiplexer 10, the element OR 11, the shapers 12 and 18 short pulses, the RS flip-flop 13, the block 14 of code generation channels and the register 17. The introduction of the element OR 19 and the formation of new functional connections increase the length of the generated code sequences. I il. 27 co 4 ate with ISO gche

Description

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The invention relates to a pulse technique and can be used in automatic data processing systems.

The aim of the invention is to increase the reliability and expand the functionality by increasing the length of the generated code sequences.

The drawing shows a structural diagram of an apparatus for generating code sequences.

The device contains a pulse generator 1, a D-flip-flop 2, an AND 3 element, a divider 4 frequencies, a delay element 5, a pulse counter 6, a block 7 cara, the first address counter 8, a first memory block 9, a demultiplexer 10, an OR 11 element, the first shaper 12 short pulses, RS-flip-flop 13, block of 14 channels forming codes, second counter 15 of address, second block 16 of memory, register 17, second

swarm shaper 18 short impulses- 25 stroke connected to the D-trigger trigger R

ow, additional element OR 19, start bus 20, bus 21. Stop, initial installation bus 22, bus 23, 24, data, address buses 25, 26, output buses 27, the output of generator 1 is connected to the first input of the element IZ, the second the input of which is connected to the output of D-flip-flop 2, the output of element I 3 is connected to the counting input of counter 15 and the input of divider 4, the installation input of which is combined with the installation input of counter 15 and bus 22, the output of divider A is connected to the input of element 5, the output of which is connected to the counting input of the counter 6 and the synchronous input of block 14, information outputs of the counter 6 are connected to the first inputs of the block 7, second

If the time interval 4t is longer than the maximum value of J taken by counter 6 (2. - 1,

The second inputs are connected to the outputs of the first memory block 9, the information is 45 D The width of the counter 6), the current inputs of which are connected to this time interval are divided by the data bus 24, the address inputs of the first memory block 9 are connected to the minimum number of intervals not exceeding the magnitude of code j. For example, with clause 4, Jf 15 with a busbar 26 and with the outputs of counter 8, the counting input of which is connected to the inverse output of the RS flip-flop 13, the direct output of which is connected to the resolution enable input of the counter 15, which is connected to the address bus 25 and the address inputs of the memory block 16, the information inputs of which are connected to the data bus 23, and the outputs are connected to the information inputs of the register 17, whose outputs

connected to the address inputs of the demultiplexer 10, the outputs of which are first to connected to the corresponding information inputs of the unit 14, and the inverse control input of the multiplexer 10 is connected to the inverse output of the comparison unit 7, the direct output of which is connected via the driver 12 to the S input RS flip-flop 13, the R-input of which is connected to

the reset input of the register 17, the installation input of the counter 6 and the output of the element OR 1, the first input of which is connected to the reset input of the block of 14 channels, the reset input of the counter 8 and

bus 22 initial installation, the second input element OR 11 is connected to the output of the imaging unit 18, the input of which is connected to the control output of the memory block 16, the output of the higher bit of counter B is connected to the input of the element OR 19, the other input of which is connected to the bus 21 stop, and you30

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2, whose synchronous input is connected to the bus 20, the outputs of the unit 14 are the output buses 27 of the device.

Each channel of the -block 14 contains, e serial T-flip-flops and a D-flip-flop.

The device works as follows.

Preliminarily, a sequence of time interval codes ut between adjacent switching outputs of the device is recorded in memory block 9 through 35 data pn 24 data. The entry is made starting from the zero address (the address code goes through the address bus 26).

If the time interval of 4t is greater than the maximum value of J taken by counter 6 (2. - 1,

45 D counter size 6), then this time interval is divided

D counter size 6), then this time interval is divided

at the minimum number of intervals that do not exceed the value of code J. For example, with n 4, Jf 15, the time interval and t 35 is divided into three intervals; 15, 15 and 5.

In a block of 16 lamies, groups of i codes are written sequentially via bus 23 data, i 1, p. Each

the group contains the channel number codes of block 14 (or, which is the same, output bus number numbers 27), which change their state at the time indicated by the corresponding time313

Noah interval At. If the time interval ut is divided into parts, then all the obtained intervals, except the last one, will become matched groups consisting of one zero code. In the code group, channel numbers are listed in arbitrary order. Channel number code contains additional information.

body bit, which finally receives group number codes

The code of each group has a single value and a zero value in other codes. This terminator of the group of codes is read from the control output of the memory block 16.

Before the device is started by a signal, the Initial setting arriving at the bus 22 is reset to zero by the counter 8, the triggers of the 14 channel block (output buses 27) are set to one value by the triggers of the divider 4 and the counter 15, and through the OR 11 element the register 17 is also reset to zero The short-trigger 13 and set to 1 all the triggers of the counter 6.

The start pulse, coming through the bus 20 to the input of the installation of D-flip-flop 2; sets it to one state, allowing the passage of pulses from generator 1 through element I 3 to the counting input of counter 15 and through divider 4 to the input of delay element 5, from which the delayed pulses simultaneously arrive at the sync input of unit 14 and to the counting input of the counter 6. The first impulse from the output of element 5 transfers all the triggers of counter 6 to the next, zero, state. The code from the outputs of the counter 6 is fed to the first inputs of the comparison unit 7. At this time, the memory block 9 reads at the zero address received from the outputs of the counter 8, the first code of the time interval t. This code arrives at the second inputs of the comparison unit 7, which reduces the code value by a unit of the least significant bit and compares the obtained result with the counter code 6. If the compared codes coincide, the signal O of the inverse output of the comparison unit 7 goes to. the inverted control input of the demultiplexer 10, and a single signal from the direct output of the comparison unit 7 is fed to the shaper 12. A short single pulse is then generated, which sets the RS-flip-flop 13 to the single state at the S input. The single signal from the direct output of the RS flip-flop is fed to the counting resolution input of the counter 15, which, under the action of the clock pulses arriving at its counting input, begins to change its state, forming a sequence of address values at the address input of the block 16. At these addresses from the output of block 16 through register 17, the address input address of the demultiplexer 10, ensuring the inverse state of the corresponding T-flip-flops of block 14 is sequentially set (through 5 information inputs of block 14).

Simultaneously with reading from the block 16 the last code of the channel number of the block 14, a single signal of the termination group sign is removed from the control output of the memory block 16. This signal is fed to the input of the imaging unit 18, from the output of which a short pulse arrives through the element OR I1

5 to the reset input of the register 17, R-input of the RS-flip-flop 13 and to the input of the installation of the counter 6 .. In this case, the register 17 is zeroed, the RS-flip-flop is set to zero and the triggers of the counter are set to 6 in 1. Signals from the direct and inverse outputs The RS flip-flop 13, respectively, stops the change in the states of the counter 15 and the counter 8 is transferred to the next state. In this case, the next time slot code it is read from the memory block 9. This code is compared by the comparison unit 7 with the codes being replaced at the outputs of the counter 6 by the action of the clock signals c. output divider 4.

The next clock pulse appearing at the output - delay element 5 is fed to the synchronous input of the block 14 of the code generation channels, providing a census of information from its input T-flip-flops to the output D-flip0

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The signals from the outputs of which the generated signals arrive at the buses 27 of the device.

If the time interval ut is divided into several intervals, then for each of the obtained intervals, excluding the last one, a group of codes consisting of one zero code is read from memory block 16. Under the action of this code, rewritten in the register 17, the demultiplexer 10 changes its zero output, which is not connected to the information inputs of the block 14 of the code generation channels.

Thus, switching on the device tires 27 at the points of rabiby or time interval it into parts does not occur.

With each clock pulse appearing at the counting input of counter 6,

This counter increases the value of the co-IQ inputs of the first memory block of the connection at its output by one. When the code reaches its value, one less than the value of the code q t, the comparison block 7 establishes this fact and the training cycle and the change in the value of the 5 signal of the signals on buses 27 will repeat.

The outputs of the first address counter, the counting input of which is connected to the inverse output of the RS flip-flop, the direct output of which is connected to the counting resolution input of the second address counter, the outputs of which are connected to the address inputs of the second unit, terminate the device when it is set to 1 high-order counter 8. This value enters through an additional, element OR 19 to the R input of the D-flip-flop 2, which then goes to the zero state, stopping the passage of the pulses of the generator 1 through the element 3. The device ends oops can also be

achieved by feeding 1 to the D input of the D-flip-flop via the bus 21 stops and the additional element OR 19.

Claims (1)

Invention Formula A device for generating code sequences comprising a pulse generator, D-flip-flop, AND element, frequency divider, delay element, pulse counter, comparison unit, first address counter, first memory block, demultiplexer, OR element, first short pulse shaper, RS- trigger, block of code-forming channels, second address counter, second memory block, register, second short pulse shaper, pulse generator output connected to the first input of the And element, the second input of which is connected to the D-t output iggera, output of AND element is connected to the counting input of the second address counter and the input of the frequency divider, adjusting input of which is combined with the installation of the second input address counter and the initial installation device bus, the output of the frequency divider coupled to an input elemenvniipi Order 4931/54 Tirrzh 900 Random polygons pr-tie, Uzhgorod, st. Project, 4 This delay, the output of which is connected to the counting input of the pulse counter and the synchronous input of the code generation channel block, the information outputs of the pulse counter are connected to the first inputs of the comparison unit, the second inputs of which are connected to the outputs of the first memory block, the address inputs of the first memory block of the connection block There are no outputs of the first address counter, the counting input of which is connected to the inverse output of the RS flip-flop, the direct output of which is connected to the counting resolution input of the second address counter, the outputs of which are connected to the address inputs of the second block PA the information inputs of the register, the outputs of which are connected to the address inputs of the demultiplexer, the outputs of which are connected to the corresponding information inputs of the code generation channel block, and the inverse the control input of the demultiplexer is connected to the inverted output of the comparator unit, the direct output of which through the first short pulse shaper is connected to the S input of the RS trigger, the R input of which is connected to the register reset input and the output of the OR element whose input is connected the codes and the reset input of the first address counter, the second input of the OR element is connected to the output of the second short pulse shaper, the input of which is connected to the control output of the second block memory, the D-flip-flop is connected to the device launch bus, characterized in that, in order to increase reliability and extend the functionality by increasing the length of the generated code sequences, an additional OR element is added to it, the input of which is connected to the high-order output of the first address counter, and the output is connected to the D input of the D-flip-flop, the reset input of the first address counter is connected to the initial setting bus device, and the installation input of the counter is connected to the output of the OR element. Subscription