SU529455A1 - Input device - Google Patents

Description

one

The invention relates to the field of computing technology and can be used in input devices.

A device for inputting information is known, comprising an information receiving unit consisting of coincidence circuits, connected to a row register, a rewriting unit and a parity decryptor connected to a row register, a binding unit, a control unit, serially connected matching unit and a clock generator, the first output of the clock pulse generator is connected to one of the inputs of the information receiving unit, the second output is connected to the control unit connected to the decoder, the third output is connected to one of the ijxoaoE rewriting information block 1J. The device allows you to control the malfunctions that occur while entering information and extract reject signals when a failure occurs.

However, the device has a low reliability of data input, which is expressed in loss of a code pulse in case of a synchronization pulse with code information pulse, which may occur as a result of irregularity of the drive mechanism, vibration of the information carrier, spread in the range of reading elements, stretching (residual deformations).

It is also known a device comprising a reading unit connected to an amplifier unit, a group of elements AND connected to a buffer memory unit connected to a control unit, and a synchronization unit 2

However, in the known device, resetting information recorded in the buffer memory block by the last pulse of a burst, and writing information into the buffer memory block with a burst of pulses, which includes the last burst of the burst, creates an indeterminate state of the triggers of the buffer memory block, which distorts code information. The use of a pulse burst generation unit and a pulse sampling unit complicates the need for an information input device.

The purpose of the invention is to improve the reliability of the device.

This is achieved by introducing a block of forming code pulses into the device, the inputs of which are connected to the outputs of the amplifier unit, and the outputs to one of the nd inputs of the group of elements I, the delay element and the gating unit whose input is connected to the delay element, and the output to others inputs of the group of elements And with the input of the control unit.

FIG. 1 shows a structural electrical circuit of the device; in fig. 2 is a time chart illustrating the operation of the device.

The device contains a readout unit 1 connected to an amplifier unit 2, a group of 3 elements And connected to a buffer memory unit 4 connected to a control unit 5, a synchronization unit 6, a code pulse generation unit 7, the inputs of which are connected to the outputs of the amplifier unit 2, and the outputs are from one of the inputs of group 3 of elements AND, the element 8 of delay and gating unit 9, the input of which is connected to the element 8 of delay, and the output to other inputs of group 3 of elements AND, and to the input of control 5.

The device works as follows

The signals read by the readout unit 1 via the P buses through the amplifier unit 2 are fed to the inputs of the block 7 for generating code pulses in duration. The code pulse shaping unit 7 consists of a trigger with separate inputs on potential elements, a delay element and three inverters (not shown in the drawing). An initial reset is applied to the zero inputs of the flip-flops of the block 7 for generating code pulses. At the single inputs of the flip-flops, code pulses of positive polarity with a crushed part come in through the inverter, differing in shape and duration with any fronts. From a single trigger output through an inverter, the negative differential is differentiated and includes a delay element, from the output of the delay element a negative impulse arrives at the zero input of the trigger and returns it to its initial state; at the zero output of the trigger, a rectangular code pulse of negative polarity is formed, with a duration T without a crushed part, which is fed through an inverter to one of the inputs of a group of 3 elements I.

The narrow sync pulse from synchronization unit 6 is delayed by delay element 8 for the time tji-y and is fed to the input of gating unit 9 executed on the same elements as the code generation unit 7, which generates a sync pulse in duration.

 the delays of the sync pulse and the duration of the sync pulse t are chosen based on the reliable gating of all code pulses on all buses. Delayed for time, | j and formed over the duration of T (the sync pulse from the output of gating unit 9 is fed to the second inputs of group 3 of the elements I and to block 5

management

Upon admission to the entrances of group 3

the elements of both the code pulses and the sync pulse at the output of a group of 3 elements and a negative pulse of duration i appears:

the single inputs of the triggers of the buffer memory block 4 are stored therein. The sync pulse from the input of the gating unit 9 enters the control unit. The control unit is formed from the falling edge.

sync pulse delayed pulses, which are used, for example, to redistribute the read information, reset, etc. These pulses from the control unit 5 are received in

block 4 buffer memory.

FIG. Figure 2 shows the variants of positioning the code pulses and sync pulses in time, explaining the choice of the duration of the code pulses g, the duration of the sync pulses (), the length of the delay line of the sync pulses (T-j (), ensuring 1) reliable operation of the buffer memory unit 4 and control unit 5:

.u

where T, is the maximum shift time between the code pulse leading the clock pulse and the clock pulse; 40 3 С U sync pulse delay time, which is equal to

where T 2, is the maximum shift time of 45 clock pulses with respect to the code pulse lagging behind the clock pulse T is part of the delay time of the clock pulse selected from the calculation of the clock pulse falling in the middle of the maximum leading clock pulse of the code pulse;

  sync pulse duration. The durations T (% and T2 (, jj are chosen so that all 55 code-shifted, signal-shaped signals that are displaced relative to each other) are reliably gated.

Claims (2)

Thus, the introduction into the input device of the block of formation of code pulses by duration, delay element 608 and gating block 9 allows to expand the functionality of these devices for cases of advanced clock code information, as well as for cases when code pulses and sync pulses they have a blown-out part, a different shape and duration, a different steepness of the front and rear fronts; increases the reliability of information input, simplifies the input scheme, which, in turn, reduces the weight and size of devices and reduces the cost of their production. Apparatus for inputting information comprising a reading unit connected to an amplifier unit, a group of elements AND connected to a buffer memory unit connected to a control unit, and a synchronization unit, characterized in that, in order to increase reliability, a unit is inserted in it generating code pulses whose inputs are connected to the outputs of the amplifier unit, and the outputs to one of the inputs of the group of elements I, the delay element and the gating unit whose input is connected to the delay element, and the output to others groups of AND rows and to the input of the control unit. Sources of information taken into account in the examination: 1.Architecture certificate number 369562, M. CL. About F 3 / O4, published O8. 02.73. 2. Author's certificate No. 356637, M. CL. G06 F3 / 04, published on 25.10,72.