SU690476A1 - Device for sequential discriminating of "ones" from n-digit binary code - Google Patents

Description

(54) DEVICE FOR THE SEQUENTIAL ALLOCATION OF A UNIT FROM A P-BIT BINARY CODE

to the first inputs of the first and second elements. And the same cell, the second inputs of which are connected respectively to the inverse and direct input information buses, the output of the first element AND of the last cell is connected to the first input of the element OR of the first cell. In addition, the known device contains a fixing unit of the last unit, which is connected to one of the inputs of one of the AND elements through the Delay circuit, and through this. The same delay circuit, the NOT element and another element And the fixing unit of the last unit is connected to the other input one of the And elements, the output of which is connected to the corresponding inputs of the auxiliary register triggers.

The disadvantage of this device is its complexity and reliability is not high enough.

The aim of the invention is to simplify the device.

The goal is achieved by introducing a trigger into the device, the output of which is connected to. the second input of the element OR of the first cell, the first input of the trigger is connected to the setup bus in the initial state. The second trigger input is connected to the clock inputs of the main register triggers and the first clock, the other inputs of the main register triggers are connected to the outputs of the corresponding triggers auxiliary registers, one input of each of which is connected to the output of the second element And the corresponding cell, the clock inputs of the auxiliary register triggers are connected to the second clocks, the output of each Trigger of the main register, except the last one, is connected to the second input of the OR element of the corresponding cell of the block Highlighted units, the main-output of the last latch register is coupled to the third input of the OR gate of the first cell. The drawing shows the block diagram of the device.

The device contains the main register 1, executed on triggers 2, auxiliary register 3, executed on triggers 4, cells of the same type 5, elements OR b, elements AND 7. and 8, trigger 9, first tact 10, second clock li, 12 reset settings:

The inputs of the flip-flops 2, 4 and 9 and the outputs of the main register I are respectively the inputs and outputs of the device.

A device for separating units from an n-bit binary code works as follows.

In the initial state, all the triggers 2 and 4 of the registers I and 3 are set to the initial, zero state, and the trigger 9 is set to one.

When selecting units from the R-bit code, the values of the source code bits are fed to the inputs of elements And 7 and 8, and the inputs of elements And 7 of the bits are supplied in the forward code, and to the outputs of elements And 8 - inverse. Since the trigger 9 is in the single state, the inputs of the element And 7 of the first cell 5 contain two enabling signals. If the value of the first digit of the source code is one, when the clock pulse is applied to the bar 10, the first trigger 4 of the auxiliary register 3 is set to one.

When a pulse is applied to the bus 1.1, the contents of the auxiliary register 3 are overwritten into the main register 1 and the trigger 9 is set to the zero state, while the output of the first trigger 2 of the main register 1 is a single signal, meaning the first unit is separated from the source code.

If the value of the first bit of the source code is zero, then two permitting signals will be present at the inputs of the AND 8 element of the first cell 5, with the result that the signal from the output of the AND 8 element enters the input of the second cell 5. Depending on which value is the code bit received for the next

cell 5, the signal from the output of the first trigger 2 is fed into the second trigger 2 or is fed to the input of the subsequent cell 5. Suppose that the values of the original bits

0 code 101 ... 01. In accordance with the above, after the first clock cycle, the first unit will be allocated, which will be indicated by the presence of a unit at the output of the first trigger 2, while the signal zero will be removed from the outputs of the subsequent flip-flops 2. Further, a third cell 5 is prepared for the selection of the next unit of the source code; a resolution signal is present at the output of the third word of trigger 2, and a unit is recorded in this trigger. Thus, the signal 00100 ... O is removed from the output of the device, which corresponds to the selection of the next unit of source code.,

Further operation of the device is similar to that described above.

Thus, the proposed device for extracting units from a binary-binary code is simpler and, therefore, more reliable than S., known by devices, for the same purpose. The absence in the claimed device of such elements; as an Exclusive OR, the delay scheme and a number of other elements not only provide simplicity and reliability of the device, but also increase the unification of the products.

Claims (2)

Invention Formula A device for sequentially allocating units from an n-bit binary code, comprising the ones executed on the flip-flops. auxiliary register, the main register connected by its outputs to the outputs of the device, of the same type, cells, each of which contains the OR element and two AND elements, with the first input of the OR element; Each cell, starting with the first one, connecting with the output of the first element And the previous cell, the output of the element OR of each cell is connected to the first inputs of the first and second elements And the same cell, the second inputs of which are connected respectively with the inverse and. the direct input data bus, the output of the first element of the last cell is connected to the first input of the element OR of the first cell, characterized in that, in order to simplify the device, it contains a trigger whose output is connected to the second input of the element OR of the first cell, the first trigger input is connected to the setpoint reset panel, the second trigger input is connected to the clock inputs of the main register flip-flops and the first clock bus, the other inputs of the main register triggers are connected to the corresponding trigger outputs The auxiliary register, one input of each of which is connected to the output of the second element AND the corresponding, cells, clocking inputs of the auxiliary regist trigger, is connected to the second clock bus, the output of each trigger of the main register, except the last one, is connected to the OR of the corresponding OR; the 7th unit allocation block, the output of the Lost trigger of the main register is connected to the third input of the OR element of the first cell. Sources of information formats taken in viimain during examination 1. USSR author's certificate No. 278215, cl. G 06 F 5/02, 05.08.70. 2. USSR author's certificate number 475616, cl. G 06 F 1/04, 03/05/73 (prototype).