SU892441A1 - Digital frequency divider with fractional countdown ratio - Google Patents

Description

(54) DIGITAL DIVIDER OF FREQUENCY WITH FRACTORAL DIVISION FACTOR

Claims (2)

The invention relates to a computing technique and can be used to divide the frequency of a pulse sequence by an arbitrary number of times. A known digital frequency divider with a fractional division factor, containing control of frequency dividers, frequency dividers with integer constant division factor, pulse counters, decade frequency dividers, switches, and adder tl3 "The disadvantage of this device is the complexity of its circuit implementation. The closest technical solution to the invention is a frequency divideth with a fractional division factor containing an accumulating adder, a main code memory block and a basic code input block 21. However, it is typical for a known divider that it is impossible to obtain an arbitrary fractional frequency divider factor, since the numerator its division ratio must be equal to the power of two, which reduces the functionality of the known frequency divider. The purpose of the invention is to expand the functionality of the digital frequency divider with a fractional division factor. This goal is achieved by the fact that in a digital frequency divider with a fractional division factor, containing a accumulating adder, the information inputs of which are connected to the corresponding outputs of the main code input block, the first inputs of which are connected to the corresponding outputs of the main code memory block connected to the control input of the accumulating adder and to the input bus, and the overflow output of the accumulating adder is connected to the output bus, additionally introduced synchronous A rep, an additional code input block and an additional code memory block whose OUTPUT is connected to the first direct inputs of the additional code input block, the second direct inputs of which are connected to the clock input of the synchronous trigger and to the input pin, the outputs of the additional code input block connected to the corresponding outputs of the main code input unit, the third inputs of which are connected to the third inverse inputs of the additional code input unit and to the output of the synchronous trigger and the overflow output of the accumulating adder with one with the data input of the synchronous trigger. The drawing shows a functional diagram of a digital frequency divider with a fractional division factor. A digital frequency divider with a fractional division factor contains the Blocks 1 and 3 of the main code memory (consisting of 2.1-2 l, switching keys) and an additional code (consisting of switching keys 4.J-4.n), block 5 of the input of the main code (consisting of a group of elements And 6.1-6.p), block 7 of the input of an additional code (consisting of a group of elements of the Ban 8,1-8.p) accumulating adder 9, synchronous trigger 1 (of type Oj, input pin 11 and output pin Well 12. At the same time, the input blocks of the main and additional code are implemented on elements that can be combined by the output to implement the OR function. The digital frequency divider with a fractional division factor works as follows. In the absence of a signal on the output bus 12, the synchronous trigger 10 generates a enable signal for the block 7 and the prohibition signal to the block 5. At the same time, the appearance of a pulse at the input bus does not 11 allow the code to be sent from the memory block through the block 7 to the input of the accumulating adder 9. The accumulating adder 9 carries out addition of the code present at its input (code written in block 3), with the contents of its memory. At the end of the pulse on the input bus 11, the result of the summing is stored in the memory of accumulating adder 9. If during this operation an overflow of accumulating adder 9 occurs, the transfer pulse at the output of the last bit of accumulating adder 9, which is the output signal of the digital frequency divider, is remembered as synchronous the trigger 10 for one period (the next after the end of the transfer pulse of the input signal of the frequency divider. In the next, after the end of the transfer pulse, the period of the input signal from The synchronous trigger 10 prevents the code from being transmitted through block 7 and allows the code to be transmitted through block 5 to the input of accumulating adder 9. In this case, if there is a pulse on the input bus 11, accumulating adder 9 will add the code present at its input (the code written in block) with the contents of its memory resulting from the previous addition. The division factor of this divider will be determined by the following expression f bx nk-кп s. m where fgy is the frequency of the input pulse sequence; output pulse frequency; code stored in memory block 3; n 1 - the capacity of accumulating adder 9; N is the number of bits of accumulating adder 9; K is a code stored in memory 1. Thus, the proposed frequency division allows obtaining a pronounced division factor with the minimum unevenness of the output signal. The invention is a digital frequency divider with a multiplicity of divisions containing an accumulator, information inputs of which are connected to the corresponding outputs of the basic code input unit, the first inputs of which are connected to the corresponding outputs of the main memory location, second turns of the basic code input unit the input of the accumulator adder and the input bus, and the overflow exit of the accumulating adder is connected to the output bus, characterized in that, in order to expand the functional Possibilities, it additionally includes a synchronous trigger, an additional code input block and an additional code memory block, the outputs of which are connected to the first direct inputs of the additional code input block, the second direct inputs of which are connected to the clock input of the synchronous trigger and to the input bus , the outputs of the additional code block are connected to the corresponding outputs of the block of input of the basic code, the third inputs of which are connected to the third inverse inputs of the additional code input block and to the output of the synchronous three and the overflow output of the accumulating adder is connected to the information input of the synchronous trigger. Sources of information taken into account during the examination 1. USSR author's certificate No. 544098, cl. H 03 K 19/00, 1975. 2. Japanese patent number 49-32462, cl. H 03 K 21/10, 1977.