SU766018A1 - Pulse repetition frequency divider - Google Patents

Description

one

The invention relates to a pulse technique and can be used in automation and computing.

A counting device with a counting factor of 2 + 1 is known, a 5-pillar counter on series-connected triggers, an additional trigger, a decoder, and a til inverter are known. Reliability is not high enough for him.10

The closest to the invention to the technical essence is a pulse frequency divider that implements the fanless design of dividers with a division factor K 2 + 1, containing successively connected triggers, the number of which depends on the magnitude of the division factor and the complementary I-Kt trigger , and the counting 20 inputs of the complementary trigger and the low-order trigger are combined with the clock input of the divider, the direct output of the low-trigger trigger is connected to the 1-input of the trigger, the subsequent discharge is -25 yes, and the inverted yield of the additional flip-flop is coupled to one input of the least significant bit flip-flop M

The aim of the invention is to expand the range of the division ratio

while improving reliability.

To do this, in the pulse frequency divider containing triggers, the inverse low-order output of each of which is connected to the counting trigger input of the subsequent discharge, and additions the trigger, the counting input of which is connected to the counting input of the trigger of the second discharge bit and to the clock input of the device, the complementary trigger is executed on a 0 trigger, the input of which is connected to the direct output of the low-order trigger, and the installation inputs of the unit of these triggers are connected respectively to the inverse output of the higher-order trigger yes and direct output 0 trigger.

The drawing shows a structural electrical circuit of the pulse frequency divider.

It contains the triggers 1, 2 and 3 of the first (junior), second, third (№) bit, trigger 4 complementary,

The operation of the device will be considered on the example of a pulse frequency divider containing three bits and one complementary trigger.

The initial 4 state of all triggers is one. At the input, the unit is set to Y, the triggers are controlled by zero.

On the arrival of the first clock pulse, trigger 4 is not ready to switch to a new state, since at its D input to the forward Q output, the states are the same.

All other triggers for the arrival of the first pulse must go to a new state, since trigger 1 is knocked over to the first pulse due to the absence of a ban on the input U1, and triggers 2 and 3 are knocked over because their inputs will change the zero state to one. trigger (with inverse output).

The table shows that the division ratio of the device in this case is 10.

For N-bit group of triggers with one complementary -trigger, the division factor to 2 + 2 is 10 for N / 3.

To divide it into five, you need two bits and one complementary triggers.

connect in a similar way to a tenth slash.

 To divide by three, no feedback is required to the input D1 of the Dt-flip-flop, and the divisor is executed on two triggers.

If we connect a non-inverse trigger for the lower-order trigger with the counting input of the trigger for the subsequent bit and direct, then the division factor will decrease by 1 to 2 + -1, for 3 (k - divider by 5 will also lose one).

By applying the proposed connections between triggers and the well-known method of modular grouping of counters, one can obtain universal pulse-frequency divider circuits, while for implementing dividers with large K (; p) fewer triggers are required compared to using the known fanless method.

Claims (2)

1. USSR author's certificate  455494, class H 03 K 23/00, 10/23/73. 2.Lainov M.L., Kachaluba V.S.Ryzhkov and.V. Digital frequency dividers on logic elements. M., Energie, 1975, p. 75