SU839068A1 - Repetition rate scaler with n and n+1 countdown ratio - Google Patents

Description

I

The invention relates to computing and automation and can be used in digital information processing equipment.

A known frequency divider comprising a controllable counter consisting of four O-triggers connected in series, the counting inputs of the first three O-triggers are combined and are the input of a frequency divider, a feedback circuit formed of three serially connected logic circuits, the first of which It has a split ratio control input. The disadvantage of this device is the limited speed due to the presence of additional delays in the passage of the signal through the feedback circuits, which create with due to the inclusion in the feedback of various logical elements, such as AND and OR.

The closest in technical essence to the invention is a frequency divider with division factors 9 or 10 containing a ring counter made on five series-connected counting triggers, on the combined counting inputs of which an input signal is fed, and the output of the fifth counting trigger is connected via an inverter the information input of the first scaling circuit, and for changing the division factor from 10 to 9, the information input of the fifth counting trigger at the expense of the switching device controlled by the external system nalom, switches from vkoda chetBeiJToro countable latch output AND gate, the first and second inputs of which are connected respectively to the outputs of the third and fourth flip-flops countable

The disadvantage of this frequency divider is also limited

speed due to the presence of additional delays in the passage of the signal through the AND element and the switching device.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that the pulse frequency divider with N and N + 1 detonation coefficients, containing triggers, the counting inputs of the first and second of which are connected to the input bus, the direct output of the first trigger is connected to the first input of the second trigger. , and a coincidence unit, 15 frequency selector on N / 2 is entered, the output of which is connected to the first input of the coincidence unit, the second input of which is connected to the direct output of the second trigger and input of frequency divider 20 to N / 2, the third input - to the control bus, and exit - with the first entrance t etego trigger to the counting input of which is connected to the inverted output of the first flip-flop, and output - with 25 the first input of the first flip-flop, a second input coupled to an inverted output of the second flip-flop.

Figure 1 shows the structural diagram of the device; figure 2 -. time diagrams explaining the operation of the device.

The device contains IK-triggers 1-3, a divider 4 frequencies on S / 2, block

5 matches, in the form of a 35 NAND element, a division division control bus 6 and an input bus 7.

Consider the operation of the device with the division factors N 10 and 40 N +.

To obtain a division factor of N 10 per control bus

6 logical level zero is applied.

In the time interval t, t О at 45 output of block 5 - the logical unit that arrives at the first input of trigger 3, trigger 1 is blocked at the first input by a logical zero coming from the output of trigger 3 50 (Fig.2.30,). The trigger 3 is in a steady state due to the absence of a pulse signal at its counting input. At the direct output of trigger 1, the level 55 of the logical unit (Fig. 1.0) is maintained, which is fed to the first input of trigger 2. The latter operates in the frequency frequency signal for two. The signal of the divided frequency is fed to the input of divider 4 by five.

The total dividing ratio of the device is

N 2 "5 10,

A changeover to the division factor is necessary on the control bus 6 by the division factor to provide a signal corresponding to the level of the logical unit (Fig. 2, time interval t t t).

For the case under consideration in time t. t, logical units over all three inputs of block 5 occur. At the time of coincidence, a logical zero appears at the output of block 5, which at the output of trigger 3 sets the level of the logical unit that arrives at the first input of trigger 1. From this point in time, trigger 1 is prepared to work on the first input in the counting mode, but still blocked on the second input. Therefore, in cycle a (Fig. 2) the division factor is kept equal to N 0. At the beginning of the new counting cycle (Fig. 2, cycle b), trigger 2 goes to state with logical unit This is the best output, which makes it possible to switch trigger 1 into the counting mode.

At time t, i.e. on the first counting pulse in cycle 5, trigger 1 goes to the state with a logical zero on the forward code, and trigger 2 goes to the state with a logical one on the forward output. But after the arrival of the second counting pulse in cycle 5 (Fig. 2, t tg), trigger 1 again switches to the state with a logical one at the direct output and a logical zero at the inverse output. As a result, the trigger 3 is switched to the state with a logic zero at the output, which blocks the trigger 1 at the first input, maintaining the level of the logical unit at its direct output. From time t5, trigger 2 is activated. Starting from this time point, only trigger 2 and divisor 4 participate in the work.

From the operation of the device, it can be seen that in cycle 5, trigger 2 is located additionally for two periods of the input signal in the state with a logical unit on the direct output, And since. divider 4 is triggered only by differences in input signals, it can be seen that cycle 5 is longer than cycle O for one period of the input signal (figure 2), i.e. the frequency division factor in cycle 5 is equal to the number of cycles during which the division factor is equal to N + 1-11, is determined by how many logical units will coincide across all three inputs of block 5, i.e. how many times in the time period to -.- trj, a logical unit is fed to the control bus 6 by the division factor. In the proposed frequency divider, the speed is increased, since the additional delays are so small that they can be neglected, therefore, there is practically no delay. There is no multiple parallel connection of the counting inputs of the triggers in the device, this facilitates coordination between the triggers and signal generators at high frequencies, which also contributes to an increase in the speed of the device.

Vpod

Claims (2)

FIG. Claims The dividers frequency division with division factors and N +1, containing triggers, the counting inputs of the first and second of which are connected to the input bus, the forward output of the first trigger is connected to the first input of the second trigger, and the coincidence unit, characterized in that In order to increase speed, a frequency divider by N / 2 is entered into it, the output of which is connected to the first input of the coincidence unit, the second input of which is connected to the direct output of the second trigger, and the input of the frequency divider to N / 2, the third input - with the bus y a systematic way, and output to the first input of the third flip-flop, a counting input coupled to an inverted output of the first flip-flop, and an output - to the first input of the first flip-flop, a second input connected to the inverted, output of the second flip-flop. Sources of information taken into account in the examination of the catalog of the company, PLESSU SEMICONDuctors, 1974, p. 215. 2. US patent No. 3456200, cl. 328-48, 1969.