SU1368986A1 - Potential recount decade - Google Patents

Abstract

The invention relates to digital automation and computing. The device contains bistable cells 3-6, including AND-OR-NOT 7 and 8 logic elements. The proposed functional connection of the circuit elements simplifies the potential recalculation decade. 2 Il. (L

Description

The invention relates to digital automation and computer technology and can be used to build fast decades of timestamp counters, pulse distributors, frequency dividers of frequency and time converters of signals into the coded equivalent of the corresponding parameter.

The purpose of the invention is to simplify and increase the speed of a potential recalculation decade.

FIG. 1 shows structural

Noah cell 3, the output of which is connected to the second input of the first group of inputs by AND of the second logical element AND-OR- -NE 8 of the second bistable cell 4, the output of which is connected to the auxiliary input of the first logical element AND-OR-NOT 7 of this bistable cell, first the input of the second group of inputs by AND of the second logical element AND-OR-NOT 8 of the first bistable element 3 and the first input of the second group of inputs by AND of the first logical element AND-OR-NOT 7 of the fourth

the scheme of potential recalculate deca- ble 15 stable element 6, output perd; in fig. 2 is a table illustrating the operation of a potential recalculation decade.

The potential recalculation decade contains a clock bus 1, an initial bus 2, and four bistable cells 3-6, each of which contains the first 7 and second 8 logic elements. The code of the first logical element AND-OR-NOT 7 is the first bistable. cells 3 is connected to the first input of the first group of inputs by AND of the second element AND-OR-NO 8 of this bistable cell, the output of which

connected to the first input of the first group of a group of inputs on the first logical input of the first logical element AND-OR-NOT 7 of this bistable h, ik and the first input of the first group of inputs on the first logical element AND-OR- -NE 7 of the fourth bistable cell 6, output which is connected to the input of the second logical element HE 8 of this bistable cell and with the first input of the second group of inputs along the first logical element AND-OR-HE 7 of the first bistable cell 3, the bus 1 of the clock signal is connected to the first inputs of the first groups of inputs along Both the first 7 and second 8 logical elements AND-OR-NOT of the second D and third 5 bistable cells and with the second input of the first group of inputs of AND the first logical element AND-OR-NE 7 of the fourth bistable cell 6, the output of the first of the AND-OR-NOT 7 logical element of the second bistable cell 4 is connected to the additional input of the second AND-OR-NOT 8 element of this bistable cell, the second input of the first group of inputs on the AND II second logical element AND-OR-HE 8 of the third bistable cell 5 and the first the input of the third group of inputs on the first logical element 7 AND-OR-NOT of the first bistable logical element AND-OR-NOT 7 of the third bistable cell 5 is connected to the first input of the third group of inputs by AND the second logical element AND-OR-NE 8 of the first bistable cell 3 and an additional input of the second logical element AND - OR-NO 8 of the third bistable cell 5, the output of which is connected to the auxiliary input of the first logical element AND-OR-NOT 7 of this bistable cell, the output of the second logic element HE 8 of the fourth bistable cell 6 is connected to the first input of the third

five

0

five

0

five

element AND-OR-NOT 7 of this bistable cell and the third input of the first group of inputs of AND the second logical element AND-OR-HE 8 of the second bistable cell 4, and the output of the second logical element AND-OR-HE 8 of the first bistable cell 3 is connected to the third input of the first group of inputs on the AND of the second logical element AND-OR-NOT 8 of the third bistable cell 5.

The bus 1 of the clock signal is connected to the second inputs of the first groups of inputs of AND 7 of the first 7 and second 8 logical elements AND-OR-NOT of the first bistable cell 3, the output of the first logical element AND-OR-NE 7 of the first bistable cell 3 is connected to the second input the first group of inputs on the AND first logical element AND-OR-NOT 7 of the third bistable cell 5, the third input of which is connected to the output of the first logical element AND-OR-NOT 7 of the fourth bistable cell 6 and the second input of the first group of inputs on the first logical element AND -Or- -n Е 7 of the second bistable cell 4, the third input of which is connected to the output of the second AND-OR-NOT logic element

the first bistable cell 3, the second inputs of the second and third group of moves on and which are connected to the first input of the first group of inputs o of this logic element, and the rety input of the second group of inputs on

This logical element is connected to the output of the second logical element NOT 8 of the fourth bistable cell 6, which is connected to the second move of the second group of inputs on AND and the first input of the fourth group of inputs on AND of the first logical element AND-OR-NOT 7 of this bistable - 15 at that, each time it changes the state and, the second input of the fourth group of inputs on and which is connected to the third move of the first group of inputs on and this is about a logical element, output

second logical element AND-OR-NOT 20 line used to form

switch bit excitation signal (marked with a dash in the same line); at a single value of the clock signal, 25 signals of bistable cells are used, having single values, and at a zero level of the clock signal, zero signals of the bistable cells of the third bistable cell 5 and the second input of the second group of inputs of the AND first logical element —OR – HE 7 of the first bistable whose - and 3, the third input of which is connected to the third input of the third group of inputs of AND of this logical element and the output of the second logical element AND-OR-NOT 8 of this bistable one and, the bus 1 of the clock signal - 30 a with the second input of the third group of moves along the AND of the first logical element AND-OR-NOT 7 of the fourth bistable cell 6, and the bus 2 initial setting when continuously following the clock signals (level drops on bus 1) with the frequency of differences following above f 1 / („, + y). i.e.

. per ./ o, -, (,, pulse frequency

on

with

The settings are connected to the auxiliary passes of the first logic elements —OR — NO 7 of the first 3, second 4, and third of the 5 bistable cells.

The work of a potential counting jade occurs according to the table of the stops (Fig. 2).

The installation of de-ada's bistable cells to the initial state is performed by feeding a single logical hijacked bus 2, the duration of this level from 4 must be at least a minimum switching delay of two (stable decade cells:

2 (b

01

with").

| de TO, and G, d - switching delays of used AND-OR-NOT elements forming the adjacent shoulders of bistable cells.

When the initial state is set, bus 1 is set to a single

logical level. Under the action of a single logical signal on bus 2 at the outputs of the trigger of logic elements 7, the level of the zero signal is set, at the outputs of logic elements 8 - the level of a single signal. Upon completion of the initial state setup, bus 2 is set to a zero logic signal.

The decade states are switched every time the signal level changes on the 1-clock bus.

only one bistable cell in accordance with the table (Fig. 2).

In the table, asterisks indicate the states of bistable cells in each

With continuous follow-up of clock signals (level differences on bus 1) with a frequency of following differences not higher than f 1 / (", + o"). i.e.

. per ./ o, -, (,, pulse frequency

on

with

bus 1 is not higher than f ,, 1 / 2C sr, decade

provides steady cyclic

change of ten states in accordance

with the state table (FIG. 2) with

reduced number of connections between

elements.

Claims (1)

Invention Formula A potential recalculated decade containing a clock signal bus, an initial setup bus and four bistable cells, each of which connects the first and second logic element, the output of the first logical element AND-OR-NOT of the first bistable cell, is connected to the first input of the first group of inputs by AND The second element AND-OR-NOT of this bistable cell, the output of which is connected to the first input of the first group of inputs of the first logical element AND-OR-NOT of this bistable cell and the first input of the first group of inputs of AND first lo nical cell 51368986f AND-OR-NOT the fourth bistable whose-AND-IPI-NOT the first bistable cell with the third entrance first ki, the output of which is connected to the input of the second logic element NOT of this bistable cell and with the first input of the second group of inputs by AND of the first logic element K-OR-NOT of the first bistable cell, the clock signal bus is connected to the first inputs the first groups of inputs on the first and second inputs of the first groups of inputs on the AND AND OR NOT logical elements of the second and third bistable cells and with the second input of the first group of inputs on the first AND AND logical gate of the fourth bistable whose-, 5 is connected to the second input of the first connected a group of inputs on the AND of the second logical element AND-OR-NOT of the third bistable cell, characterized in that, in order to simplify and improve speed, the clock signal bus is connected to the second first and second logical elements AND-OR-NOT the first bistable cell, the output of the first logical element AND-ILI-HE first bistable cell 20 25 thirty ki, the output of the first logical element AND-OR-NOT of the second bistable cell is connected to the additional input of the second element AND-OR-NOT of the bistable cell, the second input of the first group of inputs on the second logical element AND-OR-NOT of the third bistable cell and the first input the third group of inputs on the AND first logical element AND-OR-NOT the first bistable cell, the output of which is connected to the second input of the first group of inputs on AND the second logical element AND-OR-NOT the second bistable cell, the output of which is connected to with the first input of the second logical element AND-OR-NOT of this bistable cell, the first input of the second group of inputs of AND the second logical element AND-OR-NO of the first bistable element and the first input of the second group of inputs of AND the first logical element AND-OR-NOT the fourth bistable cell; the output of the first AND-OR-NOT logical element of the third bistable cell is connected to the first input of the third group of inputs by AND of the second AND-OR-logical unit of the first bistable cell and an additional input of the second logi-dts element AND-OR-NOT of the third bistable cell, the output of which 35 40 a group of inputs for the first AND-OR-NO logical element of the third bistable cell, the third input of which is connected to the output of the first AND-OR-NO logic element of the fourth bistable cell and the second input of the first group of AND inputs of the first AND-second logical element of the second bistable cell, the third input of which is connected to the output of the second logical element AND-OR-NOT the first bistable cell, the second inputs of the second and third group of inputs on AND which is connected to the first input of the first group of inputs on this logical element coagulant, and the third input The second group of inputs on AND of this logic element is connected to the output of the second logical element NOT of the fourth bistable cell, which is connected to the second input of the second group of inputs on AND and the first input of the fourth group of inputs on AND of the first logical element AND-OR-NOT of this bistable cell, the second the input of the fourth group of inputs of AND is connected to the third input of the first group of inputs of AND of this logical element AND-OR-NO of the third bi - stable cell and the second input of the second group of inputs of AND of the first logical e The element AND-OR-NOT first connected to the auxiliary input of the first logical element AND-OR-NOT of this bistable cell, the output of the second logical element NOT the fourth bistable cell connected to the first input of the third group of inputs 10 AND the first logical element I--1ShI-NOT; this bistable cell and the third input of the first group of inputs on AND the second logical element AND-OR-HP; second bistable cell, l output of the second logic element with the third entrance first the inputs of the first groups of inputs on AND per- connected to the second input of the first connected a group of inputs by AND of the second logical element AND-OR-NOT of the third bistable cell, characterized in that, in order to simplify and increase speed, the clock signal bus is connected to the second the inputs of the first groups of inputs on AND per- connected to the second input of the first first and second logical elements AND-OR-NOT the first bistable cell, the output of the first logical element AND-ILI-HE first bistable cell 0 five 0 five 0 a group of inputs for the first AND-OR-NO logical element of the third bistable cell, the third input of which is connected to the output of the first AND-OR-NO logic element of the fourth bistable cell and the second input of the first group of AND inputs of the first AND-second logical element of the second bistable cell, the third input of which is connected to the output of the second logical element AND-OR-NOT the first bistable cell, the second inputs of the second and third group of inputs on AND which is connected to the first input of the first group of inputs on this logical element coagulant, and the third input The second group of inputs on AND of this logic element is connected to the output of the second logical element NOT of the fourth bistable cell, which is connected to the second input of the second group of inputs on AND and the first input of the fourth group of inputs on AND of the first logical element AND-OR-NOT of this bistable cell, the second the input of the fourth group of inputs on And which is connected to the third input of the first group of inputs on And this logical element AND-OR-NOT of the third bi-stable cell and the second input of the second group of inputs of AND the first logical element AND-OR-NOT the first bistable cell, the third input of which is connected to the second input of the third group of inputs on AND of this logic element and the output of the second logic element AND-OR-NOT this bistable cell, the clock signal bus is connected to the second input of the third group of inputs by AND of the first logical element AND-OR-NOT of the fourth bistable cell, and the bus is connected to 1313689868 the initial installation is connected with the AND-OR-NOT first elements, the secondary inputs of the first logical and the third bistable cells. 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