SU1244757A1 - Device for distributing pulses of asynchronous system for controlling a rectifier - Google Patents

Abstract

The invention relates to the field of electrical engineering and can be used as a part of a three-phase one-channel asynchronous control system, rectifier. The purpose of the invention is to increase the reliability and stability of the operation of the rectifier. The device contains two consecutive six-bit shift registers 1,2, one (L with: 4 4 i4 SP s |

Description

the vibrator 3 and the counting trigger 4, the inputs of which are connected to the input of the device. The outputs of the counting trigger 4 are pairwise connected to the first inputs of two elements 2and 5.6. The second inputs of elements 2and 5.6 are connected to the output of the one-shot. Each of the output blocks 7, 8 contains six elements of coincidence 9. The first inputs of elements of coincidence 9 are connected to the output of the one-shot, and the second - in pairs with the outputs of the corresponding bits of registers 1,2. The outputs of the second, third and fourth bits of register 1 through the element ZILI-NOT 10 are connected to the inputs of the first bits of both registers. Using two registers instead of one ensured1

The invention relates to electrical engineering and can be used as a part of a single-channel asynchronous control system of a three-phase converter, consisting of two three-phase bridges connected in parallel but through a balancing reactor.

The purpose of the invention is to increase the reliability and stability of top performance.

FIG. 1 shows the functional scheme of the device; in fig. 2 - time diagrams that show his work.

The device for distributing control pulses contains two consecutive six-bit shift registers 1 and 2, one-shot 3 and counting trigger 4, the inputs of which are connected to the input of the device, the outputs of counting trigger 4 in pairs to the first inputs of two elements 2I 5 and 6, the second the inputs of which are connected to the output of the one-shot, two output blocks 7 and 8, each of which contains six elements 9 matches, the first inputs of which are connected to the output of the one-shot and the second - in pairs with the outputs of the corresponding bits of registers 1 and 2. The outputs of the second, third and fourth bits of register 1 through

It detects the arrival of four pulses for each thyristor during one period of network voltage. Moreover, each pulse following the first one is shifted relative to the previous one by 30 electrical degrees. Since the frequency of the pulses arriving at the clock inputs of the registers is two times less than the clock frequency, the sequence of pulses controlling the thyristors, any of the bridges are higher, they are shifted by 60 el. At the same time, the sequence of pulses coming in like thyristors of different bridges above m; 1tep are shifted relative to each other by 30 el.grad. This achieves the goal. 2 Il.

the element ZILI-NOT 10 is connected to the inputs of the first: bits of both registers.

The device generates quad pulse sequences,

of which each following the first, lags behind the previous by 30 e.grad. This ensures the inclusion of the corresponding tigors of both bridges at each period of pulsations and in the mode of intermittent current. Counting trigger 4 divides the clock frequency (input frequency, pulses Ubx) in half. The pulses of the one-shot 3 alternately pass through the elements 2 and 5 and 6 to the clock inputs of registers 1 and 2, as a result of which the contents of the registers are shifted to the right by one bit. Thanks to the feedback through the element ZILINE 10, two adjacent logical units circulate and the contents of register 2 repeat the contents of register 1 with a delay of one clock cycle,

The state of any of the 12 outputs of the device is determined by the excretion

Uu uob. tze. i 1, 2; K 1.6.

Since the unit state of each register bit is maintained for four cycles and for the period of the network voltage T is only 3

12 clock pulses are blowing Ut ;;, To for each thyristor the top of the receiver for the period T there are a number of pulses from which each follow-up is first shifted relative to the preceding by 30 al-degrees. Due to the fact that there are often I a pulses that enable the clock inputs of the registers to be twice as small as the cycles, the sequence of pulses that control the thyristors of any of the Tftn shift bridges by 60 al. At the same time, the sequence of impulses. The wounds of the bridges entering the thyristors of the same name are shifted relative to each other by 30 el.grad.

Claims (1)

Invention Formula A device for distributing pulses of an asynchronous control system of a rectifier consisting of two three-phase bridges connected in parallel through an equalization reactor containing the first sequential six-bit shift register on D-triggers, one-shot, counting trigger, two elements 2I, element ZILI-NOT and two output blocks, each of which consists of six two-input coaxial elements, the inputs of the one-shot and counting trigger are connected to the input of the device, the outputs of the counting trigger are pairwise to the first inputs of two elements 2I, the second inputs of which are connected to the output of the one-shot, the second inputs of the matching elements of the first output block are connected to the outputs of the corresponding outputs The first register of the first register, and the second, third and fourth bit of its output through the element ZILI-NOT connected to the input of the first bit, characterized in that, in order to increase the reliability and stability of work s of the rectifier, it is additionally equipped with a second sequential six-bit register on D-flip-flops, the input of the first bit of which is connected to the output of the ZILI-NE element, and the clock inputs of both registers are pairwise connected to the outputs of the 2I elements, the first inputs of the matching elements of the output blocks connected to the one-shot output; and the second inputs of the matching elements of the second output block are connected to the outputs of the corresponding bits of the second register.