SU1555855A1 - Controllable ring counter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital information processing devices, in measuring devices and computing devices. The purpose of the invention is to increase the speed and reliability that is achieved by introducing new connections and a reset bus 4. The meter also contains bits 1.1-1.N, a reset unit 2, an input bus 3, a 5.1- 5.N control bus and a single potential bus 6. In the controlled ring counter, the speed is increased by reducing the time of transient processes, and reliability is increased by reducing the number of elements used and by increasing the pulse duration from the output of the reset unit 2. 2 hp f-ly, 6 ill.

Description

ate

ate

SL

00

ate

The invention relates to a pulse technique and can be used in digital information processing devices, in measuring devices and computing devices.

The aim of the invention is to increase the speed and reliability, which is achieved by reducing the time of transients, due to JQ by increasing the duration of the reset pulse and reducing amplitude costs.

FIG. 1 shows a flowchart of a controlled ring counter; in fig. 2 shows an example of the implementation of a device bit; in fig. 3 - an example of the implementation of the reset unit; in fig. k - potential diagrams of operation of a seven-bit device; in FIG. 5 and 6 show state tables of device elements with different codes on control buses.

FIG. 1 denotes: bits 1.1-1.N, reset unit 2, input bus 25 3, reset tire k, control bus 5.1-5.N, and unit potential bus 6.

Information input of discharge 1.1 is connected to bus 6 of a single potential, information inputs of bits ™ 1.2, 1.3, 1 .N and reset unit 2 are connected respectively to outputs of discharge 1.1-1.N, clock input of reset unit 2 is connected to clock entrances

9, the second input of the first structure AND which is connected to the output of the element OR NOT 10 and the first input of the second structure OR of the element OR-AND-NOT 11, the second input of the second structure OR which is connected to the output of the inverter 8 and the first input of the second structure AND element AND-OR-NOT 9, the second input of the second structure AND of which is connected to the information input 15, the clock input AND, the input 16 of the zero setting and the inverse input 17 of the installation into the unit are connected respectively to the input of the inverter 17 and the first inputs of the OR-NE 10 and element AND NOT 12, the second inputs of which are united, respectively, with the outputs of the element AND-OR-NOT 9 and the element OR-AND-NOT 11.

FIG. 3 marked: first 18, second 19 inverters, element AND-OR-NOT 20, element OR-NOT 21, element OR-AND-NOT 22, element NOT 23, output Q 2k of the reset unit 2, clock input C 25, information input D 26 and the input R 27 of the zero setting of the reset unit 2.

In block 2 reset the output element HE 23 is connected to the output 2k and with the first input of the first structure OR of the element OR-AND-NOT 22, the second input of the first structure OR which is connected to the output of the inverter 7, with the input of the inverter 8 and with the first input of the first structure AND element AND-OR-NOT 20, second

bits 1.1-1.N and with the input bus 3, the input of the first structure And whose reset 4 is connected to the installation input zero of the reset unit, the output of which is connected to the inverse inputs of the installation in unit 1.1 1.1.N, the installation inputs zero of which connected respectively with control buses 5.1-5.N.

FIG. 2 marked: first 7, second 8 inverters, element AND-OR-NOT 9, element OR-NOT 10, element OR-AND-NOT 11, element AND-NOT 12, output Q 13 bit, yes, clock input C 14 bit , information input D 15 bit, input R 16 set zero bit and inverse input S 17 set to one bit.

In each of bits 1.1-1.N, the output of the AND-NO 12 element is connected to the output 13 and to the first input of the first structure OR of the OR-AND-NOT 11 element, the second input of the first structure OR of which is connected to the output of the inverter 7, to the input of the inverter 8 and with the first input of the first structure AND AND-OR-NOT

45

dinene with the output of the element OR-NOT 21 and with the first input of the second structure OR of the element OR-AND-NO 22, the second input of the second structure OR of which is connected to 4Q is not connected with the output of the inverter 19 and with the first input of the second structure AND of the element AND-OR- NOT 20, the second input of the second structure AND of which is connected to the information input 26, the clock input 25 and the input 27 of the zero setting of the reset unit 2 are connected respectively to the input of the inverter 18 and the first input of the OR-NOT 21 element, the second input of which is connected to the output of the AND element -OR-NOT 20, the output of the element OR-AND-NOT 22 is connected to the input ele Enta NOT 23.

FIG. k denote: potential diagrams of 28-36 signals, respectively, on the input bus 3, on the outputs of 13 bits from the first to the seventh, and on the output 2k of the reset unit 2.

FIG. 1 bits 1.1-1.N are D-flip-flops, each of which is

55

9, the second input of the first structure AND which is connected to the output of the element OR NOT 10 and the first input of the second structure OR of the element OR-AND-NOT 11, the second input of the second structure OR which is connected to the output of the inverter 8 and the first input of the second structure AND element AND-OR-NOT 9, the second input of the second structure AND of which is connected to the information input 15, the clock input AND, the input 16 of the zero setting and the inverse input 17 of the installation into the unit are connected respectively to the input of the inverter 17 and the first inputs of the OR-NE 10 and element AND NOT 12, the second inputs of which are united, respectively, with the outputs of the element AND-OR-NOT 9 and the element OR-AND-NOT 11.

FIG. 3 marked: first 18, second 19 inverters, element AND-OR-NOT 20, element OR-NOT 21, element OR-AND-NOT 22, element NOT 23, output Q 2k of the reset unit 2, clock input C 25, information input D 26 and the input R 27 of the zero setting of the reset unit 2.

In block 2 reset the output element HE 23 is connected to the output 2k and with the first input of the first structure OR of the element OR-AND-NOT 22, the second input of the first structure OR which is connected to the output of the inverter 7, with the input of the inverter 8 and with the first input of the first structure AND element AND-OR-NOT 20, second

the input of the first structure And whose soykhod first structure And whose soi

dinene with the output of the element OR-NOT 21 and with the first input of the second structure OR of the element OR-AND-NO 22, the second input of the second structure OR of which is connected to the output of the inverter 19 and with the first input of the second structure AND of the element AND-OR-NO 20, the second input of the second structure AND of which is connected to the information input 26, the clock input 25 and the input 27 of the zero setting of the reset unit 2 are connected respectively to the input of the inverter 18 and the first input of the OR-NOT 21 element, the second input of which is connected to the output of the I- element OR NOT 20, the output element OR-AND-NOT 22 is connected to the input element Not 23.

FIG. k denote: potential diagrams of 28-36 signals, respectively, on the input bus 3, on the outputs of 13 bits from the first to the seventh, and on the output 2k of the reset unit 2.

FIG. 1 bits 1.1-1.N are D-flip-flops, each of which

s

5 1555855

tory built according to the principle of master - slave (Fig. 2). Inputs 16 and 17 are the inputs, respectively, of setting the leading part to zero and setting the driven part to one.

The reset unit 2 is also a D-flip-flop, built according to the master-slave principle, in which the input of the HE element 23 (Fig. 3) of the zero setting is the input of the zero setting of the leading part.

The operation of the device is considered on an example when the number of bits is seven.

In the initial state after applying a single pulse through the reset bus k, to the D input of the D-flip-flop (reset unit 2), at its output through, 0.5Ј dts,

All subsequent cycles are similar to the first (Table 1, Fig. 3). Easy to calculate T signal processing time

in one complete cycle.

ravine

T06p O.SV AT + NCV V

ten

gde dts

This shows that the maximum frequency of the device depends on the delay time of the reset D-flip-flop, which determines the speed of the proposed counter.

FIG. 5 tab. 1-7, the repetition periods of single codes that vary from mode to mode in the range T (2 - N + l) t are shown.

The duration of the last discharge generated by the D-flip-flops pr - - - the delay time of the D-flip-20 square-shaped pulses varies from the potential, which in turn through 0.1 Ј dt, where C

ra reset (Fig. 3), formed zero

AT D-flip-flop delay time (bit

1.1-1.N) (FIG. 2), sets the D-triggers (bits 1.1-1.N) into one state, i.e., combines the counter. When a position code is supplied to the buses 5.1-5.N, which consists of a unit against the background of zeros (Fig. 5, Table 1-7), a reverse code to the positional code is set at the outputs of the device, and depending on the position O in the received reverse code, the device ensures the formation of unit codes of various lengths.

For example, if a unit of code is applied to the resetting R-input of a D-flip-flop of the first bit-1.1, then a zero potential will be established at its output after 0.5 Ј dt, all other bits will remain in the same unit state after combining . At the same time, during the arrival of pulses to the input bus 3, the D-flip-flops of the bits 1.1-1.N of the counter are written alternately with zeros. In N + 1 clock cycle through (M-1) ЈDt + cDts, and in general case through N ЈAT, since ЈATS "Ј dt is recorded in the reset D-flip-flop and through feedback with the installation inputs to 1 D-flip-flops of all bits For a time of 0.1 ddt, D-flip-flops of all bits are combined. This completes the first full cycle of forming a unit code of a given length (Fig.).

f

press to the mode in the range (1 - N) t with a constant pause equal to the duration of one measure t.

When mixing 1 in the positive code 25 to the right, the preceding bits of the counter do not participate in the formation of reduced unit codes and the potential remains high at their outputs (Fig. 5, Table 2-7).

If the position code consisting of i units in the first bits and zeros in the remaining N - i bits is applied to the buses 5.1-5.7, then we get a combination of the codes shown in FIG. 6, tab. 8th

When removing information from various outputs of the device, it can be used as a frequency divider with a variable integer-coefficient30

35

40

dividing rate: 2, 4,

N g

Thus, in the proposed device, the speed depends

45 from the delay time of the synchronous reset unit 2 and is practically independent of the counter size. In addition, in the proposed device increased reliability due to the use

50 fewer elements and the use of reset unit 2, generating a reset pulse (setting) with a duration equal to the period of the input frequency.

55

Claims (3)

1. Controlled ring counter containing input bus, control bus All subsequent cycles are similar to the first (Table 1, Fig. 3). Easy to calculate T signal processing time in one complete cycle. ravine T06p O.SV AT + NCV V ten The duration of the last discharge of D-flip-flops of the last bit pr-0 of coal-like pulses varies from press to the mode in the range (1 - N) t with a constant pause equal to the duration of one measure t. When mixing 1 in the positive code 5 to the right, the preceding bits of the counter do not participate in the formation of reduced unit codes and a high potential is maintained at their outputs (Fig. 5, Table 2-7). If the position code consisting of i units in the first bits and zeros in the remaining N - i bits is applied to the buses 5.1-5.7, then we get a combination of the codes shown in FIG. 6, tab. 8th When removing information from various outputs of the device, it can be used as a frequency divider with a variable integer-factor 0 five 40 dividing rate: 2, 4, N g Thus, in the proposed device, the speed depends from the time delay of the synchronous block 2 reset and almost does not depend on the size of the counter. In addition, in the proposed device increased reliability due to the use fewer elements and the use of reset unit 2, generating a reset pulse (set) with a duration equal to the period of the input frequency. 55 Invention Formula 1. Controlled ring counter containing input bus, control bus 7 unit, the information input of the first of which is connected to the single potential bus, the information input of each discharge, except the first, is connected to the output of the previous discharge, the output of the last discharge is connected to the information input of the reset block, the clock input of which connected to the clock inputs of the bits and to the input bus, characterized by the fact that, in order to increase speed and reliability, a reset bus is introduced into it, which is connected to the installation input of the zero block whose output is connected to an inverse With the installation inputs of 1 bit, the installation input is zero of each of which is connected to the corresponding control bus. about tl and h a- every time 2. The counter according to claim 1, S and also with the fact that the series contains two inverters, the elements AND-OR-NOT, OR-NOT, OR-AND-NOT and AND-NOT, the output of which is connected to the output bit and with the first input of the first structure OR element OR-AND-NOT, the second input of the first structure OR of which is connected to the output of the first inverter, to the input of the second inverter and to the first input of the first structure AND of the AND-OR-NOT element, the second input of the first structure -And of which is connected with the output of the element OR-NOT and with the first input of the second structure OR of the element OR-AND-NOT, the second input of the second structure OR of which of the connections with the output of the second inverter and to the first input the second structure AND element AND-OR-NOT 0 five 0 0 five five eight the second input of the second structure AND of which is connected to the information input of the discharge, the clock input, the installation input zero and the inverse input of installation 1 which are connected respectively to the input of the first inverter 1 and the first inputs of the OR-NOT element and the NAND element, the second the inputs of which are connected respectively to the outputs of the element AND-OR-NOT and the element OR-AND-NOT. 3. Counter 0 Claim 1, characterized in that the reset unit contains two inverters, elements OR OR NOT, OR NOT, OR-AND-NOT, and an element NOT whose output is connected to the output of the reset unit and to the first input of the first structure OR OR element OR - NOT, the second input of the first structure OR of which is connected to the output of the first inverter, with the input of the second inverter and with the first input of the first structure AND of the AND-OR-NOT element, the second input of the first structure AND of which is connected to the output of the OR-NOT element and with the first input the second structure OR of the element OR-AND-NOT, the second input of the structure OR whose It is connected with the output of the second inverter and with the first input of the second structure AND of the ORIL-NE element, the second input of the second structure AND of which is connected to the information input of the reset unit, the clock input and input of the zero setting of which are connected respectively to the input of the first inverter and to the first input of the OR- element NOT, the second input of which is connected to the output of the element OR, NOT, the output of the element OR-AND-NOT is connected to the input of the element NOT. 17 G6 15 W0L, MI ii P -9L 13 go t njnjnjnjTJTJTJTJTJ L h j / e / j X five 46 33 t evil / m P gz g q i RFFFP FF1FFFF house nntootififgDC / itf) ///// 00 / M 1O I П ///// 00t II 1O I I L ///// Z t f f H f | (f ff f I ff ij. Јav nntootwgodufi ifvgoj. flfffOJ Fff 1fff one pz S lfQOJ. FFFFFFF1 2 1 / QBJ. rvm 5585551 TaO / i.8 11111111 FF1111 1 1 FFF11 11 1 FFFP 1111 FFFFF 1 11 FFFFFF11 FFF FF FF 1 F ff ff ff f 11111111 FF1 1 1 111 FFF 11111 FFFFF1 7 / / FFFFF1 11 fffff11 FFFFFFF1 fffffff 11111111 TAZL.9 11111111 FFF11111 FFFP1 11 1 FFFPPf11 FFFFF11 FFFFF FF1 FFFFF FFF 11111111 FFF 11111 FFFFF 1111 FFFF ii 1 FFFFF11 FFFFFFF1 FFFffff 1 1111111 Goblea 111111 FFFFF 11 Fffff 1 FFFFF FFF FF fff f f f f 111 111 FFFF1 1 ffffff fff ffffffff fffff ff 1111111 1ffffff 1/77 Control move Fffff at 7 71FF Thailand 12 11111111 fffff 1 f Ffffff f 1 F ff Fff ff 11111111 Fffffff77 Fffffff1 Fffffff 11111111 1/77777 FF TaOf.11 11111111 FFFFF 11 / FFFFF FF11 FFFFFFF j F ff ff f. F ff 11111111 FFFFF111 FFF FF 11 FFFFFFF1 Fffffff 11111111 4 s 7 7 1 1FFF tobl and 11111111 FFPFFFF 11111111 FFFFFFFP 11111111 1 1 1 1 1 11F Fig.b 11111111