SU1670775A1 - Device for forming pulse train - Google Patents

Abstract

The invention can be used in devices for automation, control and synthesis of digital circuits. The aim of the invention is to simplify the device. The goal in the device for forming a series of pulses is achieved by introducing into it a second timer 5 and new functional connections. In addition, the device contains a single pulse shaper 2, a frequency divider 3, a first timer 4, and an OR 6 element, as well as input buses 7, 8, and 9, specifying the pulse period in the series being formed, the number of pulses in the series, and the series formation delay relative to the signal, respectively launch. 2 Il.

Description

The invention relates to a pulse technique and can be used in devices for automation, control, as well as in the synthesis of digital circuits.

The aim of the invention is to simplify the device.

FIG. 1 shows a functional diagram of an apparatus for forming a series of pulses; in fig. 2 - an example of the implementation of the first and second timers.

The device contains a start 1, a single pulse shaper 2, a frequency divider 3, the first 4 and second 5 timers, the element OR 6, the first 7, the second 8 and the third 9 input buses, the clock input 10, the first 11 and the second 12 output buses. The clock input of the device is connected to the clock inputs of the divider 3 frequency, the first timer 4 and the imager 2 single pulse. The first 7, the second 8 and the third 9 input device buses are connected respectively to the information inputs of the frequency divider 3, the second timer 5 and the first timer 4.

Input 1 start device is connected to the start input of the imager 2 single pulses, the output of which is connected to the start inputs of the first 4 and second 5 timers. The output of the first timer 4 and the inverse output of the second timer 5 are connected respectively to the first and second inputs of the element OR 6, the output of which is connected to the preset input of the frequency divider 3, the output of which is connected to the first output bus 11 of the device and to the clock input of the second timer 5, the inverse output which is connected to the second output 12 of the device. Timer 4 contains a clock input 13, a start input 14, an information input 15, an output 16. A counter 17, a comparison circuit 18, and a trigger 19.

The start 14 input of the first timer 4 is connected to the first reset input of the counter 17 and to the setup input of the trigger 19, the reset input of which is connected to the output of the comparison circuit 18. The bit outputs of counter 17 are connected to the first group of inputs of the circuit.

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we are 18 comparisons, the second group of inputs of which is connected to the information input 15 of the first timer 4, the clock input 13 of which is connected to the counting input of the counter 17, the second reset input of which is connected to the inverse output of the trigger 19, the forward output of which is the output 16 of the first timer 4 .

The second timer 5 is made similar to the first timer 4 with the exception of the output 16 connected in the second timer 5 to the inverse output of the trigger 19.

The device works as follows.

When a positive differential arrives at the start input of a single pulse shaper 2, a single pulse is generated at the output of the latter at the moment the next clock pulse arrives at the clock input 10 of the next clock pulse device.

This pulse triggers the first timer 4, at the output of which a pulse is generated with a unit level and a duration specified by the code on the third input bus 9 of the device. This duration determines the time delay of the formation of the output pulse train relative to the positive differential at the device start input. At the same time, the output pulse of the single pulse shaper 2 starts the second timer 5, setting zero potential at its inverse output. However, during testing by the first timer 4 delays due to the passage from the output of the latter through the element OR 6 signal of the unit level, the divider 3 frequencies appear in the locked state. In this case, at the clock input of the second timer 5, the pulses of the frequency divider 3 are not generated, and the second timer 5 is in the same state.

At the moment when the first timer finishes testing 4 impulse delays, a zero level signal arrives at the divider 3 preset input. This divider starts. As a result, at the output of the divider 3 frequencies, and therefore, on the first output bus of the device, pulses of a series of pulses are formed with a period defined by the division factor of the frequency divider 8, which is in turn determined by the input code on the first input bus 7 of the device.

These pulses, arriving at the clock input of the second timer 5 prepared for operation, cause the formation at the inverse output of this timer at the moment of arrival of a predetermined number of pulses of a single differential. The latter blocks the operation of the 3 frequency divider and is

the second output signal of the device. At that, the number of pulses of the formed series is set by the input code on the second input bus 8 of the device.

Timers 4 and 5 work as follows. When a single start pulse arrives at the start input 14, the counter 17 is set to the zero state, and the trigger 19 is set to one. Subsequent clocks arriving at the clock input 13 of the timer increase the contents of the counter 17. At the moment of equality of the last input code on the information input 15 of the timer, the comparison circuit 18 operates, setting its trigger pulse 19 to the initial state. Thus, at the forward output of the trigger 19 of the first timer 4, a single level pulse is generated with a duration defined by the timer input code. In the second timer 5, a similar pulse with a zero level is formed at the inverse output of the trigger 19. In this case, the counter 17 is reset

potential taken from the inverse trigger output 19.

Thus, the proposed device is simpler than the device of the prototype, since it contains a smaller number of blocks and

communications

Claims (1)

Claims An apparatus for generating a series of pulses comprising a single pulse former, a frequency divider, the first timer and the OR element, the output of which is connected to the preset input of the frequency divider, the information inputs of which are connected to the first input bus of the device, the start input of the rapper A single pulse is connected to the device start input, characterized in that, for the purpose of simplification, a second timer is entered into it, the information inputs of which are connected to the second input bus device whose third input bus is connected to the information inputs of the first timer, the output of which is connected to the first input of the OR element, the second input of which is connected to the inverse output of the second timer, the clock input of which is connected to the output of the frequency divider, the clock input of which is connected to the clock input of the device , to the clock input of the first timer and to the clock input of the generator of a single pulse, the output of which is connected to the start inputs of the first and second timers, the first and second output buses of the device facilities are connected respectively: o to the output of the frequency divider and to invert the second timer output.