RU1168U1 - Square wave generator - Google Patents

Abstract

1. A square-wave generator containing an initial state setting unit, the output of which is connected to the first inputs of the first and second controlled timers, an element NOT, whose input is connected to the output of the first timer, and the output - with the second input of the second timer, characterized in that the output of the second the controlled timer is connected to the second input of the first managed timer. 2. The generator according to claim 1, characterized in that each of the controlled timers contains a master clock generator connected to a pulse counter resolution input, an OR element, the first and second inputs of which are connected to the first and second timer inputs, and the output - to the counter installation input pulses, a controlled switching unit, the inputs of which are connected to the binary outputs of the counter, and the output - with the enable input of this counter and the timer output, and a switching control unit associated with the control input of the switching unit.

Description

TV- -

The disadvantage of the known prototype device is “that it does not solve the problem of automatically generating a sequence of pulsed rectangular signals with adjustable and not equal to each other signal durations of high (logical 1) and low (logical O) levels for one period of a regularly repeating sequence of changing output signal The result of the utility model is the elimination of the specified disadvantage of the prototype. The technical result is achieved in that in the known device C31 holding the initial state setting unit “connected to the first inputs of the first and second controlled timers” and the element NOT “whose input is connected to the output of the first timer” and the output is connected to the second input of the second timer “the output of the second managed timer is connected to the second input of the first managed timer

At the same time, “in the rectangular pulse generator, each of the controlled timers contains a timing clock generator“ connected to the pulse counter resolution input “an OR element whose first and second inputs are connected to the first and second timer inputs” and the output - with the pulse counter installation input “controlled switching unit “Input 1 of which is connected with the binary outputs of the counter“ and the output is with the enable input of the same counter and the timer output “and the switching control unit“ connected to the control input of the switching unit nations

A causal relationship between the totality of the above essential features and the achieved result is “that the new interconnection of the elements and their execution allows us to automatically generate at the output of the first controllable timer a sequence of rectangular pulses“ formed from signals of high 1 and low O levels. Moreover, “the duration of the high signal level "set by the second timer, in general, is not equal to the duration of the low level signal" set by the first timer

The drawing (Fig - 1) shows a structural diagram of a rectangular signal generator -Figure 2 shows a timing diagram of the generated pulses. The generator contains a blosos for setting the initial state 1 (block 1 can also be used to synchronize the output signals of the generator with the signals of other devices) "first 2 and second 3 controlled timers "logic element NOT 4

At the same time, t in the rectangular pulse generator, each of the controlled timers 2 and 3 contains a specific clock generator 9 and 14, connected to the V-input of the pulse counter resolution 5 and 1О, element OR 8 and 13, the first and second inputs of which are connected to the first and second timer inputs, and the output with the installation R-input of the pulse counter, the controlled switching unit 6 and 11 "whose inputs are connected to the binary outputs of the counter 5 and 1О" and the output - with the C-input of the resolution of the same counter 5 and IO and the output

of the tuner 2 and the control unit 7 and 12 connected to the control input of the switching unit 6 and II The generator operates as follows (an example of the implementation of the device on 564 series chips is considered) - Signals at the output of the OR 8 XI element and and at the output of the OR 13 X2 element Are formed in accordance with logical functions (1) and XI :: Y2 ХЗ, (1) Х2 Y1 + ХЗ, 2

 logical addition sign where

When the power is turned on (toggle switch 15 is closed — position On), the electric circuit from elements 16.17 and 18 generates a high level 1 signal at the trigger input of trigger 19, and a low level signal O at the S-input of the same trigger —Then1 at the output of trigger 19 a low level signal at the output of the element NOT 2О - a high level signal ХЗ 1 coming through the OR elements 8 and 13 to the R-inputs of the counters 5 and 10- As a result, the initial state signals Y1 Y2 O-Next are formed at the outputs of the counters, the capacitor 16 is charged and on the priority S-input of the trigger 19 signals al exponentially increases from a low level O to a high level. A single signal at the S-input of flip-flop 19 causes the output signal of the same trigger to change from O to 1 "and the signal XZ - from 1 to O" regardless of the signal level at the R-input of flip-flop 19- The HZ O signal is stored until the power is turned off - Counters

5 and 1O are set to Formation of time delays T1 and T2, respectively. The time intervals T1 and T2 are regulated by adjusting the frequency of the clock pulses of the oscillators 9 and 14 "and also by switching the corresponding binary outputs of the counters 5 and 1O with the outputs of the first 2 and second 3 timers, executed according to the commands from control units 7 and 12 in switching units

6 and 11 If the output signal of the counter 5 or 1O is zero Y1 О or Y2 О “then after a time interval T1 or T2 after changing the signal at the R-input of the counter from XI 1 to XI - О or о Х2 - 1 to Х2 ::: О at the output counter A signal Y1 - 1 or Y2 - 1 is generated, which is fed to its C-input and blocks the pulse count of the master oscillator 9 or 14. Moreover, the blocked state of the counter is stored until the Low-level signal O is generated at the R-input of the counter after mandatory zeroing counter performed when a high level 1 signal arrives at the R-input the corresponding counter, the first timer 2-Counter 5 is unlocked and starts counting the pulses t received at its V-input from the master generator 9-After counting the time interval T1t set by connecting the corresponding binary output of the counter with the help of the switch 6 by the command from the control unit 7 "at the output first timer 2 k. A high-level signal Y1 1 is pulled. The signal Y1 1 is fed to the C-input of the counter 5 "blocks the counter operation) and remains until the counter is reset to zero. At the output of the element E 4 a low-level signal X О is formed at the output of the OR element 13 a signal X2 О is generated that arrives at the installation Ft-input of the counter Yu-Counter 1О is unlocked and starts counting the pulses “received at its V-input from the master oscillator 14“ After the interval has been counted time T2 set by connecting the corresponding binary output of the counter using the switch 11 at the command of the control unit 12 "at the output of the second timer 3, a high level signal Y2 1 is generated. The signal Y2 1 goes to the C-input of the counter 1O" blocks the operation of the count chick (pulse count) and is stored until the counter is reset to zero - An XI 1 signal is generated at the output of the OR 8 element. It arrives at the counter R-input 5-The output signal of the counter 5 and the first timer 2 is reset to Yl: O-counter 5 remains blocked and signal Y1 О is stored until it is subsequently unlocked after a low-level signal XI О is received at its R-input and the time interval T1 is counted. At the output of element NOT 4, a high-level signal X 1 is generated and the device operation cycle is repeated in the sequence described above Thus, the “generator automatically generates a sequence of rectangular pulse signals with alternating adjustable and unequal durations of high and low levels of signals

Sources of information "taken into account 1- Aut-sv-USSR N 1022310" CL N OZ N 17 / OO "19822. Aut. St. USSR N 1O18167 "class N О1 Н 47 / 1В" 19В23 - Aut.St.-USSR N 12216В7 "class N О1 Н 47 / 1В" 1982 "N OZ N 17 / ОО" 19В4 "- prototype

Head of Patent Department

A-G. Sakoyan

Claims (2)

1. A square-wave generator containing an initial state setting unit, the output of which is connected to the first inputs of the first and second controlled timers, an element NOT, whose input is connected to the output of the first timer, and the output - with the second input of the second timer, characterized in that the output of the second the managed timer is connected to the second input of the first managed timer. 2. The generator according to claim 1, characterized in that each of the controlled timers contains a master clock generator connected to a pulse counter resolution input, an OR element, the first and second inputs of which are connected to the first and second timer inputs, and the output - to the installation the pulse counter input, a controlled switching unit, the inputs of which are connected to the binary outputs of the counter, and the output - with the resolution enable of this counter and the timer output, and a switching control unit associated with the control input of the switching unit.