SU1267593A1 - Pulse generator with controlled frequency - Google Patents

Description

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The invention relates to a pulse technique and can be used in the control equipment of static converters, as well as to create frequency-controlled pulse generators.

The aim of the invention is to expand the functionality of the device by providing a jump-like change in the generated frequency, followed by a gradual return of its value to the nominal

The drawing shows the functional diagram of the device.

The device contains a reference generator 1, a reversible counter 2, a programmable counter-divider 3, a feedback function block A, a discrete delay element 5, a control bus 6, a binary number reference bus 7.

The output of the reference generator 1 is connected to the clock inputs of the discrete delay element 5 and the programmable counter divider 3, the output of which through the discrete delay element 5 is connected to the clock input of the reversing counter 2, whose outputs are connected bitwise to the preset inputs of the programmable counter divider 3 and with the inputs of the block 4 feedback functions, the output of which is connected to the inhibit input of the reversible counter 2, the write enable input of which is connected to the control bus 6, and the information inputs With bus 7, set a binary number. Unit 4 of the feedback functions is a multi-input element I.

The device operates in three modes: nominal frequency., Jump to another frequency and reverse transition to the nominal frequency.

In the mode of nominal frequency of the reversible counter 2 is blocked by a signal from the output of block 4 to the input of the prohibition of the account of the reversible counter 2. At the outputs of this counter there is a binary number whose value is determined by the selected function of block 4. The pulses from the output of the reference generator 1 are fed to a clocked input programmable counter-divider 3. Programmable counter-divider 3 has a division factor of N,

determined by the binary number formed at the outputs of the reversible counter 2, which are bit-wise connected to the inputs of the presetting IH ;, Itl,,. , , Itn of the programmable counter-divider 3. As a result, the output of this counter will form a sequence of pulses, the frequency of which

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f,.,. -tg where fa is nominal hourN

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reference generator.

In the jump to another frequency mode, a permitting logic signal is generated on the control bus 6, which is fed to the enable input PE of the parallel recording of the reversible counter 2. After this signal arrives, the outputs of the reversible counter 2 generate the number that was present on the outputs DtC, on ,. .., Din reversing counter 2. Moreover, if there is a signal at the PE output that allows parallel recording, no pulses are counted. After changing the number at the outputs of the reversible counter 2, the division ratio of the counter-divider 3, and hence the output frequency of the device, will be determined by this new value of the binary number.

In the reverse transition mode to the nominal frequency at the input PE of the reversible counter 2, a signal is generated that prohibits overwriting information from the inputs D1 (/, Dt1, ..., Dtn of the reversing counter 2. This will enable the counter 2 to work, because at the Output CI the inhibit signal is absent (it is assumed that the number specified at the inputs DtO, Dt1 ,,,., Dtn differs from the number at the outputs of the reversible counter 2, at which the block 4 of feedback functions generates a signal that prohibits the account) reversible counter 2 output programmable of the counter-divider 3 by the discrete delay element 5 receives pulses from the output device.

The up / down counter 2 has an input that allows operation in forward 5 or down count mode. When the reversible counter is operating in the direct counting mode, a jump-like (+ af) increase in frequency is possible, and in mode 3.

At the countdown, a jump-like (- if) decrease in the output frequency.

Suppose that the reversible counter 2 is operating in the direct counting mode. Then the first pulse, formed at the output of the programmable counter-divider 3 after changing the signal on the control bus 6, passes through the discrete delay element 5, enters the clocked input of the reversing counter 2 and causes the binary number to increase by one, which increases the division ratio of the programmable counter - divider 3. After the next output pulse of the device, the binary number at the output of the reversible counter also increases by one. A process of consecutive unit increments of the number at the outputs of the reversible counter 2 will occur until a logical signal is generated at the output of block 4 of the feedback functions, which is fed to the counting stop input of the reversible counter 2. Thus, the device returns to the state The output frequency will take the original nominal value.

When returning from a stepwise decrease in frequency, the process proceeds similarly, except that at the outputs of the reversible counter 2, the binary number will decrease.

The duration of the return process to the nominal frequency

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is determined by the margin of numbers on the output. dah and information inputs I) t (},, ..., D1n of the reversible counter 2 (the number of clock cycles of the reversing 5 counter) and the frequency (period duration) of the pulses fed to the clocked input of the reversible counter.

Claims (1)

10 claims A controlled frequency pulse generator containing a reference oscillator, the output of which is connected to a clocked input of a programmable counter-divider, the installation inputs of which are connected bitwise to the outputs of the reversible counter and the inputs of a feedback function block characterized in that a binary number reference bus, a control bus, a discrete delay element, are entered into it, the binary number reference bus is connected to the information inputs of the reversible counter, the write enable input of which is connected to the control bus, the output of the feedback function block is connected to the inhibit input of the reversible counter, the clock input of which is connected to the output of the programmable counter divider via a discrete delay element, the control input of which is connected to the output of the reference generator.