SU1541587A2 - Timer - Google Patents

Abstract

The invention relates to the field of computing and can be used in control computing systems. A distinctive feature of the timer is that it operates both in timer mode and in the formation of a continuous pulse sequence with the simultaneous generation of pulse packets from this sequence. The duration of the pulses, the period of their following, as well as the number of pulses in the packet and the period of the following of the packets are regulated by a digital code. The aim of the invention is to expand the functionality by ensuring the formation of a packet of pulses with a variable number of pulses in a packet and with a variable packet tracking period. This goal is achieved by introducing the third register 25, the second switch 26, the third element NOT 27, the second counting trigger 28, the driver 29 of the overwriting signal, the second counter 30, and element 31. 2 Il.

Description

The invention relates to the field of computer technology, can be used in control computer systems and is an improvement of the device according to the main author. N 1322246.

The purpose of the invention is to expand the functionality due to the formation of a packet of pulses with a variable number of pulses in a packet and a variable period of the packets.

Figure 1 presents the block diagram of the timer; FIG. 2 is a diagram of the formation of a counting pulse body.

The timer contains the first counter 1, group 2 of information outputs, element I-NE 3, the first element NO 4, output 5 of the response signal, input 6 of the external clock generator, input 7 of resolution for recording commands, group 8 of inputs for setting the duration of the output pulses, second register 9, data recording resolution input 10, rewriting signal generator 11, interrupt output 12, first register 13, first switch 14, counting pulse shaper 15, multiplexer 16, one-shot 17, second HE element 18, first counting trigger 19, OR element 20 , entry 21 resolution th Eni, the output 22 of the pulse sequence, the clock generator 23, the input 24 of the recording resolution in the third register, the third register 25, the second switch 26, the third element NOT 27, the second counting trigger 28, the second driver 29 of the overwrite signal, the second counter 30, the element And 31, output 32 pulse packets,

The shaper 15 counting pulse contains the elements AND-HE 33-35, one-shot 36.

The timer works as follows. Mode I. The timer operates in the mode of counting the time interval in the same way as in the basic invention.

IT mode. If it is necessary to obtain a continuous pulse sequence with adjustable pulse duration and follow-up period, as well as pulse packets from this pulse sequence with adjustable number of pulses in the packet and the packet tracking period, the digital values of the pulse duration and pause are entered into register 9, and the third register

five

0 5 Q Q

45

five

50

55

25, the digital values of the number of pulses in the packet and the pauses between the inter; gu packets are entered. Depending on the state of the outputs of the counting triggers 19 and 28, the first and second counters 1 and 30, respectively, will first record either the value of the pulse duration, the number of pulses in the packet, or the value of the pause. If a high potential is set at the direct output of counting triggers 19 and 28 (logic level 1), then in the first counter 1 the digital value of the pulse time is recorded in input 10 of the data recording resolution, and in the second counter 30 in input 24 of the recording data resolution the digital value of the number of pulses in the packet is recorded.

The first counter 1 is in subtraction mode. The counting pulses arrive at the counting input of the first counter 1, after counting the duration of the pulse, a pulse appears at the overflow output of the counter, which arrives at the output 12 of the interruption and through the first element 18 to the counting input of the first trigger 19.

The forward exit state of the first flip-flop 19 is changed. The inverse output of the first flip-flop 19 sets the logic level 1 and the digital pause value through the first switch 14 enters the information inputs of the first counter 1 from the second register 9. This information is copied to the first counter 1 and from the output 12 of the interrupt and the cycle repeats. The pulse sequence thus formed is fed to output 22, as well as to the counting input of the second counter 30 and to one of the inputs of the And 31 element. The second counter 30 also operates in the subtraction mode. During the count of the number of pulses in the packet, the level of logic 1 is set at the direct output of the second counting trigger 28 and the second input of the element 31, and a certain number of pulses, determined by a digital code, arrive at the output of the 32 packets of pulses. After counting the number of pulses in the packet at the overflow output of the second counter 30, a pulse appears which sets the NOT 27 inverse output of the second counting trigger 28 to the logical 1 state and digital 515

The second value of the pause between the packets through the second switch 26 enters the information inputs of the second counter 30 from the third register 25. At the direct output of the second counting trigger 28, a logic level O is set and thus the flow of pulses to the output of the 32 packets of pulses is stopped. Thus, the formation of a packet of pulses is completed. After counting the pause between packets, the cycle repeats.

If there is a pulse at the read resolution input 21 or a pulse received from the interrupt output 12, and a pulse received through the multiplexer 16, the counting pulse shaper 15 waits for the pulse at the input 21, then forms a counting pulse changing the state of the first counter 1 .

When a signal is received at the read permission input 21 during a pulse at the output of the counting pulse generator 15, the AND-NE element 3 blocks the signal at the output 5 of the response signal until the end of the counting pulse. The signal at output 5 indicates the presence of reliable information at the outputs of the first counter 1.

Claims (1)

Invention Formula Timer auth. P 1322246, characterized in that, in order to expand the functionality, the timer by providing pulse packets with a variable number of pulses in the packet 0 5876 and with a variable packet repetition period, a third register, a second switch, a third element NOT, a second counting trigger, a second overwriter, a second counter, and an AND element whose output is the output of pulse timer packets, Q the first input of the element I is connected to the counting input of the second counter and with the direct output of the first counting trigger; the second input of the element I is connected to the first control input of the second  the switch and with the direct output of the second counting trigger, the inverse output of which is connected to the second control input of the second switch, the information output group of which is connected to the information input group of the second counter, the recording resolution of which is connected to the output of the second overwriting signal generator, the overflow output of the second the counter is connected to the input of the second element NOT and to the first input of the second shaper of the rewriting signal, the second input of which is connected to the recording resolution input register and with the enable input of the first register; the group of information inputs of the third register is connected to the group of information inputs of the first register, the first and second groups of outputs of the third register are connected respectively to the first and second groups of information inputs of the second switch, the output of the third element is NOT connected to the counting input second counting trigger. five 0 five 0 From 16 From go J4 Editor E. Papp Compiled by N.Toropova Tehred M. Khodanich Proofreader M. Maksimishinets Order 280 Circulation 557 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 3S This city Subscription