SU980261A1 - Pulse generator with controllable frequency - Google Patents

Description

(54) PULSATED GENERATOR WITH CONTROLLED

one

The invention relates to a pulse technique and can be used in computing.

A generator is known that contains the reference frequency gene & rator, the AND gate, the trigger, the software etch block, the logic distributor, and the pulse counter 1.

The disadvantage of this generator is the inability to lock the adjustable frequency range.

The closest in technical essence to the present invention is a pulse generator containing a series-connected clock pulse generator, a frequency divider, a pulse counter, a trigger, AND elements, a reversible counter, an AND block, an OR t program, and two G 2 J registers. .

This generator also does not allow to fix the adjustable frequency range.

FREQUENCY

The aim of the invention is to expand the range of frequency control following pulses.

The goal is achieved by the fact that the pulse generator with control e-. my frequency, containing a generator of pulses, the output of which is connected to a frequency divider, a pulse counter, a memory register, three AND elements, a trigger whose output is connected to the first input of the first AND element, the outputs of the first and second AND elements are connected to the subtracting and summing to the inputs of the reversible counter, an amplitude-voltage converter, two switches and a selector-multiplex plexer, whose information inputs are connected to the outputs of the memory register, the address inputs of the selector-ultiplexer are connected to: the outputs a reverse counter and to the bit inputs of the pulse counter, the input of which is connected to the output of the pulse generator, and the output connected to its recording input, to nei. 3. To the third input of the third element I directly and to the second input of the third element I through an amplitude-time converter, the output of the third element I is connected to the trigger input of the trigger, the second input of which is connected to the first input of the second element I, the second input of the first and the first input of the second element And is connected via a corresponding switch to the output of the divider part, and the second input of the second element And is connected to the output of the selector-multiplexer. Figure 1 shows the functional diagram of the pulse generator with controlled frequency. Pulse generator with controlled frequency contains pulse generator 1, frequency divider 2, pulse counter 3, amplitude-time converter 4, multiplexer 5 multiplexer 5, trigger 6, reversible counter 7, memory register 8, elements 9-11 And | switches 12 and 13, code writing bus 14, control voltage bus 15, output bus 16. The device operates as follows. In the initial state (when output pulses are generated at the output of the device, the value of which lies within the fixed ranges) generator 1 continuously generates stable frequency pulses that arrive at the input of divider 2 and the counter input of counter 3. From the output of divider 2 to contacts The switches 12 and 13 are given divided frequency signals (a lower frequency is necessary to organize control of the reversible counter 7). Counter 3, by connecting its output to the input of the installation record, operates in the programmed de mode. frequency player. From the output of the counter 3, the bus 16 receives pulses, the frequency of which is determined by the information inputs recorded in the counter 3, which are present in the initial state at the outputs of the digits. A counter 7 is used. The same pulses are fed to the input of the amplitude-time converter 4, the second input of which is energized from the bus 15. The control voltage determines the maximum value of the device generated / pulse repetition frequency. At the output of the amplitude-time converter .4 with a CECK pulse, which is received from counter 3, a time interval of duration is formed. 1 corresponding to the control voltage value of the bus 15. From the output. The MP1-time converter 4 signal unlocks element I 9 through one of the inputs only for the duration of the formed time interval (which in the initial state is less than the repetition period of device-generated pulses TiM), so there is a potential at the output of element 9 units of triggera 6 holds the last in zero zero scientific research institute. The memory register 8 on bus 14 is recorded, the code corresponding to the lower limit of the pulse frequency generated by the device. The same code is present at the inputs of the address of the selector-multiplexer 5. At the inputs of the selector-multiplexer 5 there are signals from the outputs of the bits of the reversible counter 7. At the second inputs of the elements 10 and 11, the resolving potentials are maintained. At the inputs of the forward and reverse counting of the reversible counter 7, there are no signals. When the switch 13 is pressed on the nefv element input element 11 begins to receive a divided clock frequency, which is fed to the reverse count input of the reversible counter 7, at the outputs of the bits of which the code changes, which leads to a change in the recorded chiol into counter 3 and, consequently, to change the output frequency of the device, pulses upwards, until the output pulse of the device coincides with the time by which element 9 opens on its second gate when the permissive time interval, generated from the output of the amplitude-time converter when the previous output pulse of the device arrives at its input. As soon as an element 9 arrives at the input of the installation of the trigger unit 6, a pulse arrives, the trigger 6 switches to the unit state and blocks the element 11 at the second input. At the same time, the flow of the pulses to the reverse counting-reversing counter 7 stops; reversible counter 7 and, consequently, an increase in the frequency of the output pulses of the device. When you press the switch 12 to the first input element And 10 and the input of the zero setting of the trigger 6 begins to receive divided clock frequency with

output of divider 2; In this case, trigger 6 is returned to the initial state and unlocks the I 11 element from the second input; from the output of the I 10 element to the direct count input of the reversing counter 7, a divided clock frequency begins to flow, which leads to code change at the outputs of the bits reversible counter 7 and therefore the frequency

; at the output of the device, up to a reduction, which will occur until the changing code at the inputs of the selector-4 < RTI ID = 0.0 > 5th < / RTI > 5 selector 5 does not match the jp code that is present at its address inputs. In this case, a voltage level appears at the output of the multiplexer 5, which blocks the element .AND 1O by stopping the input to the direct count of the reversion counter 7 divided by clock;

Claims (2)

1. Author's certificate of the USSR N9 743176, cl. N OZ K 3 / 64,1979. 2. Authorship certificate of the USSR Ms 519842, cl. N OZ K 3/72, 1976.