SU482005A1 - Voltage converter to binary code - Google Patents

Description

(54) VOLTAGE CONVERTER TO BINARY CODE FIG. 1 shows a structural electrical circuit of the prospectus; in fig. 2 - output status table decoder The voltage to binary converter contains a comparison element. 1, block 2 defining the work area, synchrosenter distributor 3, trig: hero register 4, PKN 5, block 6 for interrupting the transformation, block 7 for issuing a code, Block 6 is made as an element 8 for comparing two-digit codes, busy with a decoder 9, with a two-bit trigger remaster y 10 and an element 11 for determination being connected to element 8. jump sign. The inputs of element 11 are connected to the outputs of the decoder 9 and the outputs of the dvr register. 10. The inputs of the register U are connected to the outputs of the decoder 9, and the output of element 11 and the output of element 8 are connected .... DENAIN to the logical element I 12, the output of which is connected to the inputs of the logical elements I 13 of the two highest bits to block 7. Output element 8 is also connected to the signal output of the converter and the first inputs of logic elements AND 14, the second inputs of which are connected to the outputs of the distributor of synchronous potentials 3. In addition, the output of element 8 is connected to the second the input of which is connected via the igniter 16 to the output Element 11 and the element OR 17 to the logic elements AND 18 of the two most significant bits of block 7. The second inputs of elements AND 18 are connected to the outputs of the trigger register 10 10. The threshold elements 19, 2О, 21 included in block 2 are connected to the decoder 9, the outputs of which are connected to the control room 5. The outputs of the control room 5 are connected to a matching element 1, the output of which is connected to the trigger register 4, the outputs of the distributor 3 are connected to the control inputs of the register 4, and the outputs of the latter are connected to the control room inputs 5 and through logical elements 22 and connected to the inputs logically x elements OR 23 junior bits of Gyulok1 7, .I The outputs of elements AND 13, AND 18, as well as the same AND 14, AND 22, belonging to the same bit of block 7, are combined in pairs by the elements: OR 23. The Converter operates as follows. At the beginning of the cycle, the converted voltage is applied to the first input of the comparing element 1 and the inputs of the threshold elements 19, 20, 21. The control signal, the input of the trigger register 1O, which is part of block 6, receives a short-term / signal the beginning of the cycle .; Depending on how many threshold elements (the terminals worked for the silence started and CI1SH), the output bus of the decoder 9 was excited (or both together). As a result, the trigger register 10 records the code of the lower boundary of the working zone, within which voltage level to be converted. this higher bit, which is fed to the second input of the comparing element 1. partially, to the compensator. The voltage to be converted. The uncompressed part of the input voltage is then converted into a binary code by the method / random coding., i iKi-th sync potential with the distributor 3 is sequentially set to one state the triggers of the register 4, starting with the high-order trigger, whose outputs control the switching of the reference voltages in PKN 5. The sync potential setting to 1 regular trigger, return It does not return the previous trigger of register 4 to the zero state depending on the PW signal of the element 1. When the th switch is set to 1, the reference voltage is switched on to 1 × 5, corresponding to the weight of the i-th bit. This reference voltage is summed up PKN 5 with voltages included in the preceding | conversion cycles. If the result is a comparison of the input voltage U and the sum of the reference voltages U-. it turned out that., - r. then, at the output of element 1, corresponds to a logical unit, and (i + 1) -and the clock; 1 DfDiM The sync potential changes the coherence i of the flip-flop to O, thus disabling the I ™ e reference aplication, and sets (1 + - 1) - and a 4-to-1 trigger register. In the end of the conversion cycle, AND 22 signals are sent to the logic elements of the loop end. The same signal goes through the element OR 17 to the elements AND 18. The code formed on the decoder 9 and the trigger register 4 is given to the output of the converter. If, during the conversion cycle, there is an abrupt decrease in the voltage being converted and its output exceeds

the limits of the working zone, then; The decoder's keys 9 are changed, and at the output of element 8 for comparing two-bit.: codes, a potential appears corresponding to a logical unit that is supplied

to the inputs of elements And 14 block 7. In this. In the event of a single output, the converter carries information about the transferred g lower boundary of the working zone and the number of the conversion cycle at which the input voltage jumped. This information makes it possible to correctly place in time this sample of voltage being transformed, the value of which can be judged by; the code of the crossed border of the working area.

If there is an abrupt increase in the voltage being transformed and its output outside the working area, then with element 8 resets element 11, fta the output of which a potential appears corresponding to a logical unit. At the same time, the control potential from the output of element 8 is fed through element AND 12 to the inputs of elements AND 13 of the two most significant bits of block 7, and the code of the passed upper limit of the working zone and the cycle at which the Qt-via boundary is passed is output to the converter. After issuing the interrupt code, a transition to the beginning of the cycle occurs.

The Invention

Voltage converter to binary code, containing a comparison element,

code to voltage converter (PKN), clock distributor, trigger

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the second register and the block for code, the first input of the comparing element is connected to the source of the transformed voltage, the second is connected to the output of the PCN, and its output through the trigger register is connected to the input of the PKN and the block for issuing the code, while the output of the synchronizer potential distributor is connected with the control inputs of the trigger register, in order to increase the accuracy of the converter when the voltage to be converted changes abruptly, it contains a block for determining the working area consisting of decrypt threshold elements and interrupting unit for conversion, consisting of an element for comparison of the two-dnyh codes, two-bit flip-flop and an element for determining the jump sign, and the inputs of three threshold elements connected to a source of the converted voltage Naarah i, and outputs them through the decoder. connected to the inputs of the two most significant bits of the PKN, a block for issuing a code, and

for determining the sign by jumps through a two-digit trigger register with an element input for comparing bifasic codes, with the inputs of two higher bits, dp of the code issuing code, and element inputs, determining the second sign of the jump, whose output and output are output for two-digit codes through logical evil elements are connected to the two higher bits of the block for issuing a code, and the outputs of the sync potential limit races. and the element output for comparing two-digit codes are connected to the lower blocks of the block to issue a code. Fig Fig, 1 Signal Bbixod