SU913578A1 - DURATION SELECTOR FOR DURATION 1 - Google Patents

Description

The invention relates to automation and pulse technology.

Known pulse selector in duration, containing the element NOT, the differentiating element, the three elements And, the generator of clock pulses, ⁵ pulse counter, trigger and frequency divider [1].

The disadvantage of this device is limited functionality.

The closest to the technical essence of the present invention is a pulse selector in duration, containing a differentiating element, the output of which is connected to the first input of the first element I, and the input to the output of the element NO, the input of which is connected to the input bus and the first input of the first trigger, second _I swarm whose input is connected to the output of the OR element. and the first output is with the first input of the second element And, the second input of which is connected to the output of ge2

clock pulse and the first input of the third element is And, and the output with the counting input of the counter of pulses, the output of which is connected to the first input of the second trigger, the second input of which is connected to the first input of the frequency divider, and the output to the second inputs of the first and third elements And, the output which is connected to the second input of the frequency divider £ 2].

The disadvantage of the known device is limited functionality, due to the fact that the output of the device does not store information about the duration of the selected pulses. .

The purpose of the invention is the expansion of functionality.

This goal is achieved by the fact that the pulse selector in duration, containing a differentiating element, the output of which is connected to the first input of the first element AND, and the output - to the output of the element NOT,

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the input of which is connected to the input bus and the first input of the first trigger, the second input of which is connected to the output of the OR element, and the first output to the first input of the second element And, the second input of which is connected to the output of the clock generator and the first input of the third element And, and the output - with the counting input of the pulse counter, the output of which is connected to the first input of the second trigger, the second input of which is connected to the first input of the frequency divider, and the output to the second inputs of the first and third elements And, the output of the last of which Yuchen to the second input of the frequency divider, entered the fourth element AND, the first input of which is connected to the output of the element NOT, the second input - to the output of the pulse counter, and the output of the first input of the element OR, the second input of which is connected to the output of the first element And, the third input - with the output of the frequency divider, while the second output of the first trigger is connected to the zeroing input of the pulse counter and the second input of the second τρπι gera.

The drawing shows a block diagram of the device.

The device contains element 1 NOT, differentiating element 2, elements 3-6 AND, generator 7 clock pulses, triggers 8 and 9, frequency divider 10, element 11 OR, pulse counter 12.

Positions 13-16 denote the output bus device.

The device works as follows.

In the initial state, the triggers 8 and 9 are in the state "0 ^th . At the same time, the clock pulses of the generator 7 do not pass through the elements 4 and 5 ·

The selectable pulse with the leading edge sets trigger 9 to the state "I". In this case, from the output of the trigger 8 to the input of the element 4, the enabling voltage starts to act and the clock pulses of the generator 7 pass through the elements 4 to the input of the counter 12,

The conversion factor N of the counter 12 is proportional to the minimum selection threshold, i.e. =, Where T

period of the generator clock pulse 7 ·

If the selectable pulse does not exceed the minimum threshold of selection, then the overflow pulse of counter 12 will pass to bus 13 through element 6, the second input of which from the output of element 1 acts "allowing" voltage.

Also, the pulse from the output of the element 6 will go through the element 11 to the input of the trigger 8 and transfer it to the state "0". In this case, the voltage drop from the output of the trigger 8 sets the trigger 9, the counter 12 and the divider 10 to its original state. As a result of a double flip of the trigger 8 on the bus 14, a rectangular pulse is formed, the duration of which is equal to the minimum selection threshold.

If the duration £ £ of a selectable pulse satisfies the condition ^ hl-ΐπ, ^{then the} pulse of overflow of counter 12 transfers trigger 9, but does not pass through element 6 to output 13, since during the action at the input of the device a selectable pulse at the output of element 1 acts low voltage. In this case, the output of the trigger 9 to the input element 5 receives the "allow" voltage.

From this point on, the clock pulses of the generator 7 are fed through the element 5 to the input of the divider 10 with a division factor of 2.

Since the trigger 9 will be in the state "1" until the 5th pulse of the generator 7 passes through the divider 10, which transfers the trigger 9 to the initial state, the duration of the strobe pulse at the input of the element 3 is determined from the expression γηαχ ' = ^5T ·

At the other input of element 3, an impulse is generated, which is formed by element 2 from the trailing front selectively. pulse. When the strobe pulse and the pulse generated from the trailing edge of the selectable pulse coincide, a pulse appears on the bus 15 of element 3. This pulse also enters through the element 11 to the input of the trigger 8 and sets it to its original state.

As a result of a double flip of the trigger 8 to the bus 14, a pulse is formed, the duration of which is equal to the duration of the selected pulse. In this case, the leading edge of the pulse on the bus 14 will set the outcome5 913578 6

The state of the counter is 12, trigger 9 and divisor 10.

If the duration of the selected pulse 'ν> ta * ”, ^then R ^ez divider 10 on the bus 16 will pass the _5th pulse — ₅ pulse, which, through element 11, will transfer trigger 8 to the initial state. At the same time, at the output of trigger 8 an impulse is formed, the duration of which is equal to the maximum threshold of selection.

Thus, when a pulse sequence arrives at the selector input on the bus 14,

pulses with a duration equal to 15 the duration of the selected pulses, provided that the number of such pulses is equal to the number of pulses on the bus 15

impulses with a duration of ₂ o minimum selection threshold, when.

T · Number of such impulses

equal to the number of pulses on the bus 13,

impulses with a duration equal to the maximum selection threshold when ₂ 5

that *

The number of such pulses is equal to the number of pulses on the bus 16. The use of the proposed introduced element I and new connections favorably distinguishes the proposed selector of pulses, since at the output of the device _; information about the duration of the selected pulses is stored, which in turn provides an extension of the functionality of the device.

Claims (1)

Claim Pulse selector by duration, containing differentiating the element whose output is connected to the first input of the first element AND, and the input to the output of the element NOT, whose input is connected to the input bus and the first input of the first trigger, whose second input is 'connected, n' to the output of the OR element, and the first output with the first input of the second element And, the second input of which is connected to the output of the clock pulse generator and the first input of the third element And, and the output to the counting input of a pulse counter, the output of which is connected to the first input of the second trigger, the second input of which is connected to the first input of the divide The frequency is set, and the output is with the second inputs of the first and third element I, the output of the last of which is connected to the second input of the frequency divider, characterized in that, in order to expand its functionality, the fourth element I is entered into it, the first input of which is connected to the output the NOT element, the second input is with the pulse counter output, and the output is with the first input of the OR element, the second input of which is connected to the output of the first AND element, and the third input is connected to the output of the frequency divider, while the second output of the first flip-flop is connected to zeroing m input pulse counter and With the second input of the second trigger.