SU1663760A1 - Pulse generator - Google Patents

Abstract

Usage: in the pulse technique, for the formation of pulse signals modulated on the basis of the following frequency. SUMMARY OF THE INVENTION: A frequency divider, a parallel code shaper, the first and second OR elements, whose first inputs are connected to the second input bus and the control input of the clock generator, are entered into the generator, the second input of the first OR element is connected to the output of the one-time comparison unit, the output of the first element OR is connected to the installation input of the first counter, the second input of the second element OR is connected to the transfer output of the second counter, and the output of the second element OR is connected to the write enable input of the second counter the clock output is connected to the clock input of the first counter, the output of the logic switch is connected to the clock input of the second counter, the second input of the logic switch is connected to the output of the bit comparison unit through the frequency divider, the third input of the logic switch is connected to the third input bus, the output of the parallel code generator connected to the information inputs of the second counter, the outputs of the bits of which are connected to the second inputs of a one-bit comparison unit. 1 il.

Description

The invention relates to a pulse technique and can be used to generate pulse signals modulated on a tracking frequency.

The purpose of the invention is to expand the functionality of the generator due to the possibility of programmatically changing the period of the generated pulses.

The drawing shows an electrical block diagram of the device.

The pulse generator contains a clock generator 1, the first and second counters

2.3, unit 4 in bit comparison, with the first inputs connected to the outputs of the bits of the first slider, and the logical switch 5 connected to the first input bus 6, frequency divider 7, parallel code shaper 8, first and ator elements OR 9, 10, the first inputs of which are connected to the second input signal 11 of the control signal and the control input of the clock generator 1, the second input of the first element OR 9 is connected to the output of the bit comparison unit 4, the output

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the first element OR 9 - to the installation input of the first estimator 2, the second input of the second element OR 10 is connected to the transfer output of the second counter 3, and the output of the second element OR 10 - to the write enable input of the second counter 3, the output of the clock generator 1 is connected to the clock input of the first counter 2, the output of the logical switch 5 to the synchronization input of the second counter 3, the second input of the logic switch 5 through the frequency divider 7 is connected to the output of the bit comparison unit 4, the third input of the logic switch 5 s Connected to the third input bus 12, the outputs of the parallel code generator 8 are connected to the information inputs of the second counter 3, the bit outputs of which are connected to the second inputs of the bit comparison 4.

Logic switch 5 can be performed on element 2I-2I-OR, the first inputs of the elements are respectively the first and third inputs of the logic switch, the second input of the first element AND the second input of the logic switch and connected via an inverter to the second input of the second element I. °

The generator works as follows.

Before the generation begins, the input bus 11 sends a setup signal in the form of a logical unit, which through the OR element 9 sets the counter 2 to the zero state, and through the OR element 10 to the counter 3 enters the number N from the output of the imager 8. If there is a logical unit at the control input of the generator 1, its operation is stopped and at its output a logic zero level is set.

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After removing the setup signal from the input bus 11, the clock generator 1 begins to generate clocks with a period of T, which is fed to the input of counter 2. After the passage of N pulses, the numbers stored in counters 2 and 3 become equal and at the output of block 4 This comparison establishes the level of the logical unit, which, through the element OR 9, the counter 2 is set to the zero state. After this, a new cycle of counting clock pulses to the number N begins. As a result, pulses with a period of follow up are generated at the output of block 4, which are fed to the input of divider 7 having division factor K.

After the passage of K pulses with a period Ti, the output of the divider 7 is formed

impulse, which, in the presence of a logical unit on bus 12, passes through logical switch 5 and arrives at the clock input of counter 3. As a result, the number (N + 1) is fixed in counter 3. Next, the analog is generated by K pulses with a following period ( N + 1), after which the number (N + 2) is set in the counter 3, and the newly formed series of pulses has the following period

(M + 2). This process of forming a series of K pulses continues until counter 3 has the number 2P, where n is the number of bits of the binary counter 3. After the counter 3 is filled,

The output of the transfer is a pulse that, having passed through the element OR 10, is fed to the input of the recording resolution. As a result, the number N is re-entered in the counter 3 and a new cycle of formation of pulses modulated by the tracking frequency begins. In this case, the minimum duration of the period of the generated pulses is equal, and the maximum is (2n-1). In each series with the same

the repetition rate contains K pulses. The period of the next series of pulses differs from the period of the preceding series of pulses for the period of the clock pulses T.

In this case, the period increment occurs according to a step-linear law.

In order to obtain a different law for changing the period of the generated pulses, the logic bus zero is applied to the input bus 12. In this case, the input bus 6 is connected to the synchronizing input of the counter 3, and the output of the divider 7 from the input of the counter 3 is disconnected. In this case, the nature of the change in the period of the following

The pulses are determined by pulsed control signals fed to the input bus 6 from an external pulse driver (not shown). Thus, if there is a voltage of a logical unit on the input bus 12, the period of the generated pulses changes according to a stepwise law with the quantization step T. With a voltage of logical zero on the input bus 12, the change in the duration

period is produced by pulse signals from the input bus 9.

Claims (1)

(54X57) PULSE GENERATOR containing a clock generator, the first and second counters, a bitwise comparison unit, the first inputs connected to the discharge outputs of the first counter, and a logical switch connected to the first input bus, characterized in that the possibility of programmatically changing the period of the generated pulses, a frequency divider, a parallel coder