SU554618A1 - Preset Pulse Counter - Google Patents

Description

one

The invention relates to the field of pulsed technology.

A preset pulse counter is known, which contains counting cells, clock drivers, indicators of tens and units, control circuits.

This counter has insufficient accuracy 1.

Also known is a counter containing counting cells, a plurality of comparators, selection devices, each of which is connected to comparators, a synchronization device connected to a step control circuit that controls the respective counting cells and comiarators 2.

This counter has a complex scheme and does not provide the necessary speed.

A preset pulse counter is known, containing sequentially connected phase-counting counting cells, the inputs of which are connected to the nerve output of the clock pulse generator, to which the control generator control input is connected, the code setting unit, the inputs of which are connected to the output of the constant generator, pulse frequency divider connected between the input of the first phase of pulsed counting cell and the second output of the clock pulse generator, a delay line connected to the control inputs of the s Adani code and pulse distributor.

This counter does not have sufficient speed.

In order to improve speed, a pulse counter with presetting is introduced to the logical code comparison elements and a logic element I, and the first input of each logical element of the code comparison is connected to the output of the corresponding phase-pulse counting cell, the second input of each logic element of the comparison code is connected to the corresponding output of the master unit , and the outputs of the logic elements of the comparison codes are respectively connected to the third inputs of the logic elements of the comparison codes ceding and Valid bits logicheskog AND gate, the second input of which is connected to the output of divider

frequencies, and the output is connected to the delay line and the information input of the pulse distributor.

The drawing shows the structural electrical circuit of the proposed counter.

The counter contains phase-impulse counting cells 1-3, a divider 4 imulse frequencies, a shaper of 5 clock pulses, a code setting unit 6, a constant generator 7, a delay of 8 delays, a distributor of 9 imulses, logic elements 10-12 of a comparison of coils, And 13, input 14, outputs 15-18, control inputs 19-21 of unit 6, generator 7, distributor 9, respectively.

The counter works as follows.

Before starting the operation, the counter is reset, in block 6 the specified multi-digit numbers in the ir code are set, as a result of which the specific inputs of the generator 7 are connected to the second inputs of each element 10-12 of the code comparison through block 6. code of the first multi-bit number.

 Input 14 receives input signals generated by shaper 5 in two sequences of pulses, one of which is fed to the input of the divider 4 frequencies and, divided by the divider 4 frequencies, arrives at the input of counting cell 1. Counting cells 1-3 begin to fill. Another sequence of pulses is applied to the second counting inputs of each counting cell 1-3 and the input of the generator 7. The division factor of the 4 frequency divider is equal to the division factor of one counting cell.

Thus, the sampling rate of counting cells is an order of magnitude higher than the counting frequency. Counting cells 1-3 and generator 7 are polled with the first pulse train.

Geoerator 7 generates signals at control outputs. The signal from the p-th control output of the generator 7 corresponds to the overflow signal of one counting cell.

The signals from the selected control outputs of the generator 7 through the block 6 are fed to the second inputs of the corresponding elements 10-12 of the comparison codes, the first inputs of which receive overflow pulses from the corresponding counting cells I, 2 or 3. However, none of the elements 10-12 of the comparison codes does not work.

Element 12 comparison codes does not work, because the signals arriving at the first and second inputs do not match in phase, and elements 10 and 11 due to the lack of an enable signal coming from the output of each of the elements 11 and 12 comparison codes (allowing signals formed when the elements 12 and 11 of the code comparison are triggered).

In the process of filling the counting cells 1-3 with a sequence of pulses, the phase of the overflow pulses from the polled counting cells 1-3 and the signals from the selected generator outputs 7 entering the first and second inputs of the comparison code elements 10-12, respectively, begins to shift.

When the phase of the signal coming from the selected generator output 7 coincides with the signal of the corresponding overflow of the counting cell 3 of the pulse sequence, the code comparison element 12 triggers and outputs a enable signal to the code comparison element 11.

Thus, the comparison of the first selected multi-digit number during the operation of the device is performed from the highest counting bit.

Let us consider in detail the process of comparing the programmed multi-digit number. Counting cells 1–3 are filled with pulses. Upon reaching the high counting cell 3, the value corresponding to the value of the first selected multi-digit number, preparation for the operation of the code comparison element 12 is carried out, and when polling the high counting cell 3 and the generator 7 by a sequence of pulses, the overflow signal from the high counting cell 3 arrives at the first input of the element 12 comparison codes, which coincides in phase with the signal coming from the selected output of block 6 to the second input of the element 12 comparison codes, which is triggered and produces an enabling signal and enabling input comparator element 11

codes. Counter cells 1, 2 are continued to be filled with pulses.

Upon reaching the counter cell 2, the value corresponding to the value of the programmed value, in this counting order, is.

There is a preparation for triggering the code comparison element 11, and when polling counting cell 2 and generator 7, a sequence of pulses overflows the signal from counting cell 2 to the first input of code comparison element 11, which coincides in phase with the signal from the selected generator output 7 on the second input of element 11, the last one is triggered and gives an enable signal to the enable input

item 10 comparison codes. Counter 1 continues to fill with pulses.

Upon reaching the counter cell 1 of the value corresponding to the value of the programmed value in this counter bit, preparation for the operation of the code comparison element 10 is carried out. When polling counting cell 1 and generator 7 by a sequence of pulses, the non-execution signal from counting cell 2 is fed to the first input of the code comparison element 10, the signal coincides in phase with the signal from the selected generator output 7 to the second input of the code comparison element 10, which operates and outputs enable signal at first

input element And 13, and at its second input receives a signal from the output of the divider 4 frequency.

Element And 13 is triggered and issues a signal to the information input of the distributor 9,

to the corresponding output of the device and to the input line 8 delay. The signal from the output line 8 delay, affecting the control input of the distributor 9, connects the output element And 13 to the next output device

and is fed to the control input of block 6, which connects to the second inputs of each element 10, 11, 12 comparison codes determined from the control outputs of generator 7, providing bitwise comparison of the code

second mogram dyogo number.