SU1169170A1 - Digital code-to-pulse repetition frequency converter - Google Patents

Abstract

DIGITAL CODE CONVERTER TO FREQUENCY OF PULSE MONITORING, which contains a memory register, the inputs of which are connected to the corresponding buses of the input code, the main unit of code comparison, executed on A, decadal comparison elements, pulse generator, frequency divider, the output of which is connected to the output bus. A pulse counter made in / for decades, the transfer output of each of which, except the junior and senior, is connected to the counting input of the corresponding subsequent decade, and the information outputs of the decades are connected in reverse order to the first inputs of the corresponding decade comparison block of the code comparison unit, the second inputs which are connected to the corresponding outputs of the memory register, the recording resolution of which is connected to the transfer output of the high decade of the pulse counter, and the prohibition element, the first input of which is connected yield older decadic element code comparing unit comparing a third input of each ..-%. GZ f ... Cf / ---. The tenth decadic comparison element, which, besides the youngest, is connected to the output of the corresponding preceding decade comparison element of the code comparison block, and the third input of the lower decade comparison element is connected to the logical 1 setting bus, characterized in that, in order to expand the functionality of the converter, into it a pulse separation unit, a pulse shaper, an AND element, an OR element, and an additional code comparison block performed on the L / decade comparison elements, the first (O inputs which x is connected to the first inputs of the corresponding decade elements of the comparison of the main block of comparison codes, the second inputs are connected to the corresponding additional buses of the input code, the third input of each, except the youngest, is connected to the output of the corresponding previous decade element of the comparison of the additional block compared to the codes, and the third input of the younger deso the frame element of the comparison of the additional code block is connected to the installation bus of the logical 1, while the output of the higher decade element of the comparison additional audio code comparing unit is coupled to the input of the pulse shaper, the output of which is connected to the reset input of the decade younger and counting input of the second decade counter pulses, wherein the pulse generator output coupled to an input pulse separation unit whose first output is connected to the counting input of younger

Description

the decade of the pulse counter and the second input of the inhibit element, and the second output — with the first input of the element I, the second input of which is connected to the control bus, and the output to the first input of the element OR, the input of which is connected to the output of the prohibition and the output frequency divider input.

The invention relates to a pulse technique and can be used, in particular, as an output node of various digital control systems of automation. The purpose of the invention is to expand the functionality of the converter. The drawing shows a structural electrical circuit of the converter (for the case of converting a three-bit binary-decimal code). The converter contains a memory register 1 designed for storing the converted code in binary-decimal cells 2-4, code comparison block 5, decadic comparison elements 6-8 of which are executed, for example, on elements 2-2-2-ZILI, add wearable code comparison unit 9, consisting of three decadal elements 10-12 comparison, pulse counter 13, executed over three decades 14-16, shaper 17 pulses, pulse generator 18, pulse separation unit 19, prohibition element 20, element 21, element OR 22, frequency divider 23, input code bus 24-26 , additional buses 27-29 of the input code, control bus 30, output bus 31 and installation bus 32 logical 1. A convertible three-digit binary-decimal code, 210, 10 is fed through buses 24-26 to the input of memory register 1, s the output of which the reverse code is applied to the second inputs of block 5 of code comparison, the first inputs of which are code from counter 13 pulses in reverse order (i.e., decades of memory register 1 and counter 13 pulses are connected to block 5 of code comparison in reverse order) The return code from the code point generator (, V10 + N, 0 10 ° through the additional buses 27-29 of the input code is fed to the inputs of the additional code comparison unit 9, similarly to the main code comparison unit 5. The transfer output of the decade 15 of the counter 13 pulses is connected to the counter the input of decade 16, the transfer output of which is connected to the input of recording resolution of memory register 1, the first output of prohibition element 20 is connected to the output of the senior decade comparison element 6 of block 5, the third inputs of decade comparison elements 6 and 7 are connected respectively to the outputs of elements 7 and 8, and the third input of the element 8 - with the installation bus 32 logical 1. The third inputs of the decade elements 10 and 11 of the additional comparison block 9 of the code comparison are connected respectively with the outputs of the elements 11 and 12, and the third input of the element 12 - with the installation bus 32 logical 1. The output of the higher decade comparing element 10 of the additional block 9 of comparing codes is connected to the input of the pulse shaper 17, the output of which is connected to the reset input of the lower decade 14 and to the counting input of the decade 15 of the counter 13 pulses. The output of the pulse generator 18 is connected to the input of the pulse separation unit 19, the first output of which is connected to the counting input of the lower decade 14 of the counter 13 and the second input of the inhibiting element 20, and the second output to the first input of the 21 element, the second input of which is connected to the control bus 30 and the output to the first input of the element OR 22, the second input of which is connected to the output of the inhibiting element 20, and the output to the input of a frequency divider 23, the output of which is connected to the output bus 31. 3 Every decade of the code comparison unit works as follows . If the Ng code at the first input is any, from the decades of the code comparison block is less than the YD code at its second input ,. then at the output of this decade, a logical O signal is applied. The appearance of a logical 1 at the output of the decade depends on the magnitude of the signal at its third input. If the third input of a decade is acted upon by a logical O signal, then logical 1 is at the output of this decade at NO N. + 1. If the signal of the logical 1 acts on the third input of this decade, then its output is logical 1 in terms of Ng Nd. The prohibition element 20 transmits the pulses of the reference frequency f if the output of the high decade of the code comparison block 5 receives a logical O at its input, and does not pass the pulses of the frequency f if the output of the logic 1 signal is applied. The pulse separation unit 19 is designed to generate two pulses sequences whose frequencies are equal in absolute value to the frequency of the reference generator / U / and the pulses in which are shifted relative to each other by half a period. The Converter operates as follows. In the initial state, the code in the counter 13 pulses is zero. As the pulses of the reference frequency fg arrive at the counting input of the lower decade 14 of the counter 13 of pulses, the code in the latter starts to increase. When the code is increased in the lower decade 14 of the impulse counter to the value (N553 +1) at the output of the higher decade element 10, the comparison of the additional block 9 of the code comparison shows the signal logic 1, on the front of which the pulse former 17 will generate a pulse arriving at the counting input of the second decade 15 of the counter 13 pulses and the reset input of the younger decade 14 of the counter 13 pulses, the code in which again begins to increase from O to (N5331 + 1). So it will continue until the code in the middle decade 15 of the counter 13 pulses reaches the value (Nj,;, +1), i.e. it is not yet logical for 1 at the third input of the senior decade comparison element 10 additionally 70. 4 th unit 9 comparison codes. This reset of the lower decade 14 of the counter 13 pulses occurs when the code of this decade reaches the value N ,,. . When the tenth pulse arrives at the counting input of the second decade 15 of the pulse counter 13, the code in the latter will become zero, as the output of the second decade comparison element 11 of the additional block 9 of the code comparison is logical O, and the code in the lower decade 14 of the pulse counter 13 rises from ABOUT (TO) Thus, it is possible to follow the work of the younger decade 14 of the pulse counter 13 until it is zeroed, i.e. until the transfer pulse appears at the output of the higher decade 16 of the pulse counter 13. After that, everything repeats from the beginning. Neither T between two transfer pulses at the output of the pulse counter 13 represents a single conversion cycle (period). The conversion cycle duration is determined by the code applied to the input of the additional block 9 of code comparison with the code setter for buses 27-29 T N T T S where TO is the period of the following reference frequency pulses, i.e., from one transfer pulse at the output of the pulse counter to another, N arrives at the counting input of this counter (Jd the number of reference frequency pulses. Moreover, the required number of pulses is provided due to the controlled reset of the first decade 14 of the counter 13 of pulses. The reset control is carried out as a result of a serial analysis of the code in the counter 13 pulses and the code received from the code master. Because of this younger decade, 14 counters 13 pulses count to (Nj, 3, + 1) or to Njjg. The result of the bit code analysis coming from the code master is determined by the expression aA lX,) (N2,) + N ,,, 10 (N2, c,) N ,,, + (N, -f1) -N + N, V 00-N.,) (10-N ,,). ) Thus, changing the time of the conversion cycle can be changed.

The conversion of the N code to the pulse frequency lies in passing through the prohibition element 20 in one cycle the conversion of the number of pulses equal to the value of the code N to be converted. The prohibition element 20 is controlled by signals from the output of the senior decade comparison element 6 of the code comparison unit 5.

At the beginning of each conversion cycle, the code in the counter 13 pulses is zero. If the code to be converted is not zero (N ,,,), then the output of all decade elements of the comparison block 5 of the code comparison block is a logical signal O, which from the output of the high decade 6 of the code comparison block 5 allows the passage of the reference frequency pulses f to the output of the element 20 zhsretta As the pulses of the reference frequency arrive (5 at the input of the youngest decade 14 of the counter 13 of pulses, the code in the latter starts to increase, and when it reaches the value () at the output of the older decade comparison element 6 of the code comparison unit 5, the logical 1 will be denied pulses of the reference frequency through element 20, i.e., one miscalculation of the lower decade 14 of the counter 13 pulses at the output of the prohibition element 20 will pass (Nj + l) of the pulse.After resetting the lower decade 14 of the counter of 13 pulses at the output of the higher decade 6, al logic O and the passage of the reference frequency f pulse will again be allowed through the element 20, ban.

Thus, the prohibition element 20 will pass packets of () pulse until the code in the second decade 15 of the pulse counter 13 reaches the value (. After that, the third input of the senior decade comparison element 6 of the comparison unit 5 compares the codes with a logical 1 and through the element 20 will pass packets of N, a pulse, i.e. depending on the state of the previous decades 7 and 8, the high decade 6 of the code comparison block 5 thus controls the prohibition element 20 that the packets pass through it (Nj + 1) or by Nj pulses. And the total number

impulses, the passage of w; its one cycle through the element 20 of the prohibition, is equal in magnitude to the code being converted. The transfer pulse of the pulse counter 13 records the converted code in memory register 1 and the conversion cycle is repeated. The order of alternation of bursts of () and Nj pulses is the result of a bit analysis of the converted and current codes in the counter of 13 pulses and is determined by the expression

(N + 1) (N2 + 1) (N, i + 1) N, + + (N, + 1) N2 + N-.- NjdO-Np (10-N,) (3)

For example, when converting a code, expression (3) takes the form N (36 + 2-4) .7. + (3-5 + 2-5), i.e. through element 20, in one conversion cycle, 6 packets of 3 pulses will first pass, then 4 packs of 2 pulses, and this distribution will be repeated 7 times. After that 5 packs of 3 pulses and 5 packs of 2 pulses of each will pass, this distribution will repeat 3 times. In the next conversion cycle, the code for the order of impulse placement is exactly the same

Using the principle of bitwise analysis allows us to evenly distribute the pulses of the reference frequency f over the entire conversion period. At the output of the transducer, these pulses are fed through a divider 23 of the reference frequency, the use of which allows to improve the arrangement of the pulses of the output sequence in time.

If a logic signal O acts on the control bus 30, then only the pulses from the output of the prohibition element 20 are passed to the input of the reference frequency divider 23 of the reference frequency OR 22.

The frequency at the output of the converter is

g N N

9l1x t. Kt. N C H o ass

where K is the division factor of the divider of the reference frequency; N is the value of the current to be converted. If logical 1 is acting on the control bus of the AND 21 element, then the frequency f pulses through the AND 21 element and the YI 22 element begin to flow to the reference divider 23

7

frequencies. In this case, the frequency at high speed will transform

f f about. + it to

notak like) f ;; / jf | / fj, then the expression (5) can be represented as follows:

f fo HZ.

W-r can be seen from the expression (6), with the value of the converted code

2f 5aA output K

where d, (with the maximum possible frequency at the output of the converter, i.e. all pulses of the reference frequency pass to the divider 23 of the reference frequency, and with codes, the frequency of the max.

The division factor K of the reference frequency divider is chosen based on the given f Qi j. :

f,

 4OVC

TO

2f

1169170

In a known converter, the frequency varies from 0 to f, and

 M U k С

the value of f (j, aicc corresponds to a fixed code (for the case of converting a three-bit binary binary code).

In the proposed converter, the output frequency can vary both from O to fj. ,,,, and from -, O

Max

0 „

-makhe

In addition, in the proposed converter, the maximum output frequency can be obtained for any desired value of the code to be converted. For this. N .. code set

equal to the value of the code being converted, which requires obtaining the maximum frequency at the output of the converter.

0

For example, if | 1 MHz,, N ,, 750 and on the bus 30 controls the operation,

If logical 1, then when the code changes from 0 to J 750 fj, it will change from 4000 Hz to 8000 Hz. With the values of the code being converted 750 g N 999, the output frequency of the transducer will also be equal to 8000 Hz.

Claims (1)

DIGITAL CODE CONVERTER IN THE FREQUENCY OF PULSE FOLLOWING, containing a memory register, the inputs of which are connected to the corresponding input code buses, the main code comparison unit, executed on ft decade comparison elements, a pulse generator, a frequency divider, the output of which is connected to the output bus, a pulse counter, made on / with decades, the transfer output of each of which, except the youngest and oldest, is connected to the counting input of the corresponding subsequent decade, and the information outputs of the decades are connected in the reverse order to the first inputs of the corresponding decade comparison elements of the code comparison unit, the second inputs of which are connected to the corresponding outputs of the memory register, the recording enable input of which is connected to the transfer output of the high decade of the pulse counter, and the prohibition element, the first input of which is connected to the output of the senior decade decade comparison element of the comparison unit codes, the third input of each ten-day comparison element of which, except the lowest, is connected to the output of the corresponding previous ten-day comparison element and code comparisons, and the third input of the lowest decade-long comparison element - with a logical 1 setup bus, characterized in that, in order to expand the converter's functionality, a pulse separation unit, a pulse shaper, an AND element, an OR element, and an additional code comparison unit are introduced into it made on TSdekadnyh comparison elements, the first inputs of which are connected to the first inputs of the corresponding ten-day comparison elements of the main block code comparison, the second inputs are connected to the corresponding additional by the input code bus, the third input of each, except the junior, is connected to the output of the corresponding previous ten-day comparison element of the additional code comparison unit, and the third input of the lower decade decimal comparison element of the additional code comparison unit is connected to the logical 1 setting bus, while the output of the senior decade element comparing an additional code comparison unit is connected to the input of the pulse shaper, the output of which is connected to the reset input of the younger decade and the counting input of the second steps of the pulse counter, and the output of the pulse generator is connected to the input of the pulse separation unit, the first output of which is connected to the counting input of the lowest decade of the pulse counter and the second input of the inhibit element, and the second output is connected to the first input of the And element, the second input of which is connected to the control circuit ^ output-to the first input of the OR element, the second input of which is connected with the output of the inhibit element, and the output is the input of the frequency divider.