SU1280693A1 - Device for generating pulse trains - Google Patents

Abstract

The invention can be used in computing, where it is necessary to form a variable pulse sequence. The aim of the invention is to increase the reliability of the device. To achieve this goal, elements 15,16, inverters 17,18 and delay lines 12,13,14 are introduced into the device for forming a series of pulses. The device also contains multi-input elements AND 1.2, a group of 3 pulse counters with a variable division factor, blocks 4, 5 elements AND, trigger 6 and a ring shift register 10. This device allows equipment to be reduced by 50% by simplifying the process of controlling the formation of a series of pulses and pauses between them. 2 cl. about s (l

Description

The invention relates to a pulse technician and can be used in computing devices where it is necessary to form a variable pulse sequence.

The purpose of the invention is to increase the reliability of operation of the device by simplifying the pause and number of pulses in the series control schemes.

Fig. 1 shows a functional diagram of a device for forming a series of pulses; Fig. 2 shows time diagrams of its operation.

A device for forming a series of pulses contains two multi-input elements AND 1 and 2, a group of 3 pulse counters with a variable conversion factor, two blocks 4 and 5 of elements AND, trigger 6, first and second outputs 1, respectively connected to the first inputs of the first . and the second elements And 7 and 8, the second; the inputs of which are connected to the input bus 9, and the outputs are the outputs of the device, the ring shift register 10, the input of which is connected to the bus 1 1 of the initial installation, and the outputs through a series-connected first block / 4 A elements and a group of 3 pulse counters with a variable factor recalculation is connected to the inputs of the first multi-code element AND I, with the help of which a series of pulses are formed on the first and pauses on the second outputs of the device, the second inputs of the first block of 4 elements AND are interconnected, the setting input d group 3 pulse counters with a variable conversion factor, connected to the output of the second element And block 5, three delay lines 12-14, two elements AND-NOT 15 and 16, two inverters 17 and 18, the input of inverter 17 is connected to the output of a multi-input element AND 1, and the output is connected to the first input of the NAND 15 element: the output of which is connected to the R input of trigger 6 and the first input of the first I element of block 5, the output of which through the delay line 12 is connected to the first input of the second element And block 5, and the second input is connected to the bus 11 of the initial installation and the first in Odom third AND unit 5, the second: - having an input connected to the output of AND-NO element 16, vtorm input of the first AND gate unit 5

and the input of the ring register 10 shift, and the output is connected to G, the input of the trigger 6, the first output of which through line 13 of the delay is connected to the second input of the element fi-HE 15, and the second through line 14 of the delay to the first input of the element AND NOT 16, The second input is through an inverter 18 connected to the output of a multi-input element And 2, the inputs of which are connected to the outputs of a group of 3 counters with a variable conversion factor, which form a series of pulses on the second and pauses on the first outputs of the device, and the input bus 9 is connected to the second inputs And ntov unit 4.

The device works as follows.

Claims (1)

The initial setup signal coming from the bus 11 (Fig. 2a) transfers the ring register 10 to the initial state. The initial setup signal through the third element And block 5 (Fig. 2c) passes to the input of trigger 6 and sets it to the single state (Fig. 26) so that at its output there is a single potential allowing the passage of the input pulses through the AND element 7 to the first output of the device for forming a series of pulses, which determines the formation of the first series of pulses on this output. The zero potential at the other output of the trigger 6 (Fig. 2b) prohibits the passage of input pulses through element 8 to the second output of the device for forming a series of pulses, which determines the formation of the first pause on this output equal in duration to the first pulse series on the first code. The initial setup signal through the second element I of block 5 is fed to the installation inputs of a group of 3 counters with a variable conversion factor and zeroes the contents of all the counters. So, after the passage of the initial setup signal, the trigger 6 is in the unit state, all the counters of group 3 are cleared, in the first discharge of the ring shift register 10 one is written, and in all other bits - zeros. The input signals to the bus 9 begin to arrive at the moment of termination of the Ngchalnaya installation signal (Fig. 2a and 2g | .. 3) The input signals go to the 9Gfg.2g bus to the second inputs of the AND elements of block 4, the first inputs of which are connected to the bits of the Ring register 10 The single potential at the output of the first bit of register 10 and zero in all other outputs determines the passage of the input pulses through the first of the AND elements of block 4 to the counting input of the first counter of group 3 of counters. and my counter grows until its 3 output shows a potential of zero (fig.2n), which through the multi-input element And 2 enters as a unit potential at the input of the element AND-NOT 1 6 (fig.2p) but, since at its first input there is a low-level potential coming from the output of flip-flop 6 (fig.2b) through delay line 14 (fig.2l), the output of the AND-16 element (fig.2r) changes the signal level do not occur. The first counter from the group of 3 counters continues to count the input pulses, until its e-output has a zero potential (fig.2d) which through the multi-input element AND 1 and the inverter 7 falls in the form of a unit potential (FIG. 2e) to the first input of the element AND-NOT 15. As the second input of the element AND-NOT 15 is the unit potential, thanks to the single potential at the output of the trigger 6 ( Fig. 2b) at the output of the element AND-NOT 15, the potential of the zero level (Fig. 2g), which hits the input of the trigger 6, transfers it to the zero state (Fig. 26), and passes through the first element And block 5 (phT -.Z3) delay line 12 (Fig. 2k) and the second element And block 5 will reset the group of 3 meters. This device completes the formation of the first series of pulses on the first output and pauses on the second. Line 12 of the delay is inserted into the device to ensure stable operation of the trigger 6, since the elements entering the device may have different response times. The delay value is shown in FIG. 2, as the zero state of the trigger 6 determines the beginning of the formation of the first series of pulses at the second output of the device from the output of the element 8, 93, since at its first input there is a high level potential, at the same time the first input element And 7 is a low level potential that prohibits the passage of pulses through it, which determines the beginning of the formation of a pause at the first output. Since the state of the ring register 10 shift does not change, the first counter of the group of 3 counters again begins to calculate the pulses arriving at its counting input through the first element AND of block 4 via bus 9 (Fig. 3g), while at its 3 output nb Vits zero potential (fign), which passed through the multi-input element And 2 and the inverter 18 comes in the form of a single potential to the second input element AND-NOT 16 (fig.2p). At the first input element AND-NOT 16 there is a single potential, which comes from the second output of the trigger 6 (FIG. 2B) through the delay line 14 (FIG. 2L). Since the first and second inputs of the element AND-NOT 16 have a single potential, then its potential has a low potential (Fig. 2p), which enters the input of the ring register 10 and the unit from its first bit shifts into the second, defined thereby selecting the next counter, which determines the duration of the next series and pauses of the pulses at the outputs, at the same time, the low potential from the output of the AND-16 element, passed through the third element of AND 5 (fig.2c), will set the trigger 6 into one state (fig.2b), and entering the installation entrances of groups s 3 meters through the first AND gate unit 5 (fig.2z), delay line 12 (fig.2k) and a second AND gate unit 5 resets the counters of group 3 meters. At this device ends the formation of the first series of pulses at the second output and pause at the first. Subsequently, the operation of the device proceeds along the same path, while the unit shift over the bits of the ring register 10 determines the selection of a counter from group 3 of counters, according to the conversion factor of which a series of pulses is first generated at the first output and a pause at the second and (after a change of state trigger 6) pause at the first and a series of pulses at the 5th second output. From the last bit of the ring register 10, the unit is copied to the first bit and the operation of the device is repeated. Line 13 and 14 of the delay in the device to ensure its correct operation in the case when the first and second outputs need to form the same duration of a series of pulses and pauses between them, In this case, the corresponding inputs of many elements And 1 and 2 are connected to one output of the corresponding counter of group 3 counters. When the meter counts to a predetermined value, then at the outputs of the multi-input elements And 1 and 2 there will simultaneously be a zero potential, which, having passed through the corresponding inverters 17 and 18, is shown in the form of a single potential, at the inputs of the elements AND-HE 16 and 15. Depending on the state of trigger 6, on one of the elements IS-NE 15 or 16 there will be a resolving unit potential, and on its output it will be zero, which will change the state of the trigger 6. As this time zeroing groups of 3 counters does not happens, then on one and exits ele Copies NAND 15 or 16 (depending on the state of trigger 6) may form over the fur, resulting in a false triggering of the device. Due to lines 13 and 14 of the delay, this is not the case since the delay line delays the enabling signal appearing on one of the outputs of trigger 6 after it has been redirected for a time equal to 2 (Fig. 2) until the group 3 of the counters is reset. The invention The device for forming a series of pulses, containing two multi-element AND elements, a group of pulse counters with a variable conversion factor, two blocks of elements And, a trigger, the first and second outputs of which are connected respectively to the first inputs of the first and second elements And, the second inputs of which are connected with the input bus and the outputs are the outputs of the device, a circular shift register, the input of which is connected to the bus of the initial installation, and the codes through the first block of elements connected in series Both and a group of pulse counters with a variable conversion factor are connected to the inputs of the first multi-input element And that are responsible for forming a series of pulses on the first and pauses on the second outputs of the device, the second inputs of the first block of elements And are connected to each other, the second inputs are also interconnected groups of pulse counters, with a variable conversion factor, characterized in that, in order to increase reliability, it additionally introduces three delay lines, two NAND units, two inverters, an input of the first of which is connected to the output of the first MI element, and the output is connected to the first input of the first INE element, the output of which is connected to the R input of the trigger and the first input of the first element And the second block of elements And whose output is connected to the first input through the first delay line The second element And the second block of elements And whose code is connected to the installation inputs of a group of pulse counters with a variable conversion factor, and the second input is connected to the bus of the initial installation and the first input of the third element a And the second block of elements And, the second input of which is connected to the output of the second element AND-NOT, the second input of the first element And the second block of elements And and the input of the annular shift register, and the output connected to the S-input of the trigger, the first output of which through the second delay line is connected to the second input of the first NAND element, and the second output is connected via the third delay line to the first input of the second NAND element, the second input of which is connected via the second inverter to the output of the second multi-input element I, whose inputs are connected to the second group of outputs of a group of pulse counters with a variable conversion factor, - and the input bus is connected to the second inputs of the elements And the first block of elements I. -bJ b 6 d and P pr-lj P eleven and 0mg 2