SU813747A1 - Device for detecting pulse code combinations - Google Patents

Description

(54) DEVICE FOR DETECTION OF IMPULSE CODE COMBINATIONS

one

The invention relates to impulse technology and can be used, in particular, in devices for compacting digital information.

A device for allocating code-coded pulse combinations is known, comprising a shift register, a counter, and a match element 1.

The disadvantage of this device lies in the fact that it does not allow the allocation of m identical, next-order pulse combinations.

The closest technical solution to the proposed one is a pulse selector of a given code combination containing elements I, a counter, a clock generator, an inverter, an actuating element.

This device detects pulse code patterns that follow another at the beginning of each information transfer cycle 2.

However, the known device has two significant drawbacks. The first of these is that the device is capable of extracting only the simplest impulse code combination of the form 10.

 However, in the series, for example, when synchronizing information compacting devices, it becomes necessary to select a more complex n-bit combination that repeats m times or more (for example, type 1000). The probability of the random occurrence of this combination in the composition of the impulses of the operating information is rather small. The second disadvantage is the low noise immunity of the device due to the fact that the clock frequency signals arrive at one of the inputs of the And element, and the input information signals, strobe frequency, arrive at the other input of this element with a delay due to the And element and the inverter. As a result, short-term spurious pulses are generated at the output (on the leading edge of the clock frequency), which nullify the counter at each data transfer clock.

The aim of the invention is to increase the noise immunity while extending the functionality.

Claims (2)

The goal is achieved by the fact that a device containing two inverters, a counter, has an output of the first element AND, and a counting input - the output of the first digit of the shift register, the input of which is connected to the output of the second element, one of the inputs of which is connected to the input bus, three consecutively included one-shot are added, the OR element and the decoder, the inputs of which are connected to the outputs of the shift register, while one of the inputs of the decoder through the first inverter is connected to the input bus and the decoder outputs are connected to the inputs of the OR element, the output of which is connected to one of the inputs of the first element AND, the other input of which is connected to the output of the third one-oscillator, the input of which is connected to another input of the second element And, and the input of the first single-oscillator is connected via the second inverter to the clock frequency bus and to the input of the shift register | -a. FIG. 1 is a block diagram of the device; in fig. 2 - time diagram, explaining his work. The device contains an input bus 1, which is connected to one of the inputs of the second element I 2 and the input of the first inverter 3, the shift register 4, the inputs of the second inverter 5 and the clock frequency 6, are connected to the inputs of the decoder 7 and the counting input counter 8, connected to the output of one of the bits of the shift register 4. The inputs of the element OR 9 are connected to the outputs of the decoder 7, and its output to one of the inputs of the first element AND 10. The input circuit consists of three serially connected single vibrators I, 12 and 13 are connected to the output the second inverter 5, and the output of the one-shot 13 - to the second input of the first element And 10, the output of which is connected to the zero input of the counter 8, containing the output terminal 14. The device operates as follows. The input bus 1 receives P-bit pulse code combinations containing K-ones and P-Z-zeros. For example, with K 1 and 4, the pulse code combinations are of the form 1000. This device detects repeated m times times, without gaps, pulse code combinations and outputs a signal to the output key of 14. Depending on the values of rn, 11, K in the device can change only the size of the shift register 4, e.fviKocTb of the counter 8 and the number of inputs of the element OR 9. In this case, the main structural links and nodes remain unchanged. In the case when the input bus 1 receives impulse code combinations of the type 1000, repeated m times times, without gaps, all the combinations of this type, repeated less than once or m times, but not more times, but with gaps, this device not detected. Therefore, the principle of operation of this device is that all sets of combinations in the amount of N 2-1, where P 4, except for the set of combinations of type 1000, are decrypted and zeroed in counter 8. The set of m combinations of type 1000 is not decrypted and during the existence of counter 8 does not zero. In this case, the combination of type 1000 is counted. Counter 8 operates modulo t, i.e., after repeating another series of combinations of type 1000, it outputs a signal to output terminal 14. In the event that at least one other device arrives at the input time, different from view 1000, the combination, this combination is decrypted and zeroed the counter 8. All previously received combinations of type 1000 are not counted. When using the timing diagram, the device works as follows. When passing through the communication channel, the pulse combinations are shifted in time, subjected to various interferences, but this is to ensure that the shift register 4 works correctly, these pulse combinations are gated. Gating is performed as follows. From the input band 1, the received code combinations are fed to the input of the second element I 2 (Fig. 2 a). The second input of the second element And 2 receives short strobe pulses from the output of the one-shot 12 (Fig. 2e). The one-shot 12 starts from the one-shot 11 (Fig. 2e), which, in turn, is started negative. coming through the second inverter 5 (Fig. 2 g) from the bus clock frequency 6 (Fig. 2 c). The delay time determined by the one-shot 11 is chosen to be slightly less than half the period of the clock frequency, and therefore the pulse gating of the combinations is carried out approximately at the center of each pulse (Fig. 2 l). In addition, the delay time of the one-shot 11 is selected based on the need to start at one point the one-shot 13, which produces pulses (FIG. 2 m) that prohibit the passage of spurious pulses from shift register 4 (FIG. 2 n). From the output of the second element And 2, the gates of the input pulse combinations (Fig. 2 L), corresponding to the number of units in the combination, are fed to the input of the four-bit shift register 4 and are recorded in it (Fig. 2, f, 3, k). The input of the shift register 4 receives pulses from the bus clock frequency 6 (Fig. 2). The signal from the low-order bit of the shift register 4 is fed to the input of the counter 8, which counts the number of resolved combinations of the form 1000. The pulse combinations recorded in the shift register 4 are fed to the input of the decoder 7, the output of which the signal occurs if Shift register 4 recorded either a prohibited combination or a zero combination (no input signal). The pulse in the first discharge register of shift 4 is shortened due to gating (Fig. 2 g), therefore, during reception of a given pulse combination of type 1000, shift register 4 for a certain period of time At is in zeroed state. Consequently, at the output of the decoder 7, a pulse of duration D1 arises, which through the coincidence element And 10 is fed to the obnu ing input of the counter 8 (Fig. 2 o) In order to neutralize this signal, to the input of the decoder 7 instead of the signal coming from the first digit of the shift register 4, through the first inverter 3, a signal from the input bus 1 is supplied. From the output of the element OR 9, the signal through the first element AND 10 is fed to the obnuzhny input of the counter 8. Only the lower digit of the shift register 4 is connected to the counting input of the counter 8, therefore the pulsed combination and, containing a unit in other bits, are not affected by the counter 8, and signals containing more than one unit, through the decoder 7, the elements OR 9, AND 10, nullify the counter 8. When the device receives the required combination 1000, the input the input of the first element And 10 receives a low potential; therefore, a low-level signal also appears at its output, permitting the operation of the counter 8 (Fig. 2 o). After the counter 8 counts the specified m pulses, the pulse 14 does not appear at the output, which is formed by known techniques and means (Fig. 2). When an impulse interference type 1000 appears in the composition of a resolved combination (Fig. 2a), a tamping pulse appears at the tamping input of the counter 8 (Fig. 2 o). When the shift register 4 is working, at the moments of rewriting at the outputs of the shift register 4, interference pulses (short-term voltage surges) are formed, which can reset counter 8 during the counting of allowed combinations of the form 1000. These emissions (Fig. 2n) are generated as a result of transients in the triggers of the shift register 4. In order to neutralize the harmful effects of these emissions. To the second input of the first element I 10, negative prohibiting pulses are generated, which are formed by the one-shot 13 (Fig. 2 m), launched from the single-impactor 12, which produces strobe pulses. Thus, the device makes it possible to increase the accuracy of detected m identical and alternate repeated n-bit pulse code combinations. The use of this device gives a significant technical effect in terms of improving the noise immunity during the phasing of multi-channel markerless compaction devices and pulse information. The invention is a device for detecting pulse code combinations containing two inverters, a counter, to the zeroing input of which the output of the first element I is connected, and to the counting input - the output of the first digit of the shift register, to the input of which is connected the output of the second element And, one of the inputs which is connected to the input thickness, characterized in that, in order to increase the noise immunity while enhancing the functionality, three successively added adnibrators are added to it, The OR element and the decoder, the inputs of which are connected to the outputs of the shift register, one of the inputs of the decoder through the first inverter connected to the input bus, and the outputs of the decoder connected to the inputs of the element OR, the output of which is connected to one of the inputs of the first element AND, the other input connected to the output of the third one-shot, the input of which is connected to another input of the second element And, and the input of the first one-vibrator through the second inverter is connected to the clock frequency bus and to the input of the shift register. Sources of information taken into account in the examination 1. Shberskiy V. I. Fundamentals of technology for the transmission of discrete messages. M., 1973, p. 297, fig. 5.28. 2. USSR author's certificate number 634453, cl. H 03 K 5/13, 04.01.77. B./