SU1275531A1 - Device for digital magnetic recording - Google Patents

Abstract

The invention relates to instrumentation and allows to reduce the error of magnetic recording. With the frame pulses from the output of the AND 6 element received at the input of the register 8 along their falling edge, the information available in the register 8 is shifted by one bit and appears at its output signal, characterizing the first of the bits recorded in it.

Description

Yu

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The signal through the AND 4 element is fed to the EI INP of the 14 level converter. Information from the output group of the logging station 17 is connected to the inputs of the OR element 15, the output of which forms a pulse, the negative 14 of which triggers 14 to single.

1275531

To eliminate the interfering impulse, the frame impulses from the synchronization output of the recording unit 2 are fed to the input of the element 6 through the delay line 11. A high logic level from the direct output of the flip-flop 13 is fed to the input of the 3-level converter. 4 il.

This invention relates to digital magnetic recording.

The purpose of the invention is to reduce the error in magnetic recording.

. Figure 1 shows a block diagram of a proposed digital magnetic recording device; Figures 2 and 3 show temporal stress plots at various points of the device; 4 shows an embodiment of a level converter.

The device contains amplifiers 1, recording unit 2, level converter 3, AND 4-6 elements, registers 7 and 8, memory block 9, delay lines 10 and 11, counter 12, triggers 13 and 14, element OR 15 and inverter 16.

I

The device works as follows.

Analog information from the logging station 17 is fed to the inputs of the amplifiers 1 of the device being the first inputs. Amplifiers 1 bring the amplitude of the analog signal to the value necessary for normal operation of the analog-to-digital converter of recording unit 2. For accurate analog information to the depth of the well from which it comes, the second outputs of the logging station 17 constantly have a digital code for obtaining information, which, when changed, is accompanied by a synchronizing pulse from the third output of the logging station 17. At the same time, the digital parallel depth course recorded in register 7 for further registration; Block 2, during registration, sequentially polls signals at its inputs, converts them into a digital code, and records, for example, on a magnetic information carrier. In a single survey of all analog signals at the inputs, the recording unit 2 generates a frame synchronizing pulse (Fig. 2a), coming through line 11, and opens an AND 6 element transmitting information to the register 8 to the counter 12, which passes each N pulse to its output arriving at its input (figb).

On the leading edge of this pulse, the register 8 records in the parallel code information from the register outputs. 7 and memory block 9. The number of information inputs of register 8 is equal to the sum of register bits 7 and the bits of memory block 9.

Claims (1)

Then, using frame pulses from the output of element 6 (fig. Bv), which arrive at the input of the shift of register 8 on their falling edge, the information available in register 8 is shifted by one bit. After that, the information output of register 8 appears signal characterizing the first bit recorded in it. This logical level (fig.Za) through the open element And 4 is fed to the first input of the level converter 14. To arrange additional information to the depth, which has an integer value, for example, 10, 120, 430 m, etc., information from the corresponding number of minor bits from the second output group of the logging station 17 is input to the inputs of the OR 15 element. all its inputs are zero logic levels; at its output there will also be a zero level, i.e. a pulse is formed (fig.2g), the negator3 .1 by the differential drop of which trigger 14 is set to one with a stop (fig.2d). As a result, the input of the setup to: Zero of the trigger 13 appears a single level, which removes the prohibition from the operation of the trigger 13. At its counting input, a personnel pulse is received, on the leading edge of which the trigger 13 is set to the single state (Fig. 2e), B As a result, the resolution is removed from the second inputs of the AND 4 and 6 elements. The AND 6 element does not transmit the frame pulse to the input of the second register 8 and the counters 12. To eliminate a short interference pulse that may occur at the output of the 6 And element due to the delay time of triggers EPA 13 vertical pulses output from the synchronization unit 2 records fed to a first input of AND gate 6 via the delay line 11. The last delay time is longer than the start time of the first 13 flip-flop. A high logic level from the npjmoro output of the trigger 13 is applied to the second input of the converter of the 3rd level (Fig. 36). With the arrival of the next frame pulse, on its leading edge, the trigger 13 is reset to the initial position (Fig. 2e). As a result, the resolution is removed from the second input of the converter of level 3 and a negative differential sets the trigger 14 to its initial state (Figure 2d). The invention The device for digital magnetic recording, containing amplifiers, the inputs of which are the first group of inputs of the device, and the outputs are connected 31 to the inputs of a recording unit, to the control input of which the output of the level converter is connected, the first input connected to the output of the first And element, the first a register whose information inputs are the second group of device inputs, and the input input is connected to the output of the second element AND, the first input of which is the third input of the device, characterized in that reduce the error of the digital magnetic recording, a second register, a memory block, two delay lines, a counter, a third AND element, two triggers, an OR element and an inverter are entered into it, with the memory block outputs and the first register outputs being connected to the first and second groups of inputs of the second register, the output of which is connected to the first input of the first element And, the output of the third element is connected to the input of the shift of the second register and to the input of the counter; whose output is connected via an inverter to the first input of the second element And through n The first delay line is connected to the second register input input, the output of the recording unit is connected to the first input of the first trigger and connected via the second delay line to the first input of the third And element, the first output of the first trigger And connected to the second inputs of the first and third elements, And the second output of the first trigger connected to the second input of the level converter and to the first input of the second trigger, the output of which is connected to the second input of the first trigger, the inputs of the OR element are connected to the buses of the second group of device inputs, and you the stroke is connected to the second input of the second trigger. and and Ui . 2 .} (Jskt U Both FIG. 3 l , t 3 / v - /  Unu / n Vyzeo Sxff32 Bjfodf .