GB1458994A - Demodulators for frequency shift keyed signals - Google Patents

Abstract

1458994 Frequency discriminators SIEMENS AG 26 June 1974 [2 July 1973] 28285/74 Heading H3A An f.m. demodulator, e.g. for a data receiver, comprises: a counter ZA which measures the interval between consecutive flanks of received signals by counting up a plurality of times from a starting-value to a maximum count; a control circuit ST which, at each flank, emits a transfer pulse which writes the instaneous count into a store SD and an erasing pulse which resets the counter; a digital/analogue converter DA coupled to the output of the store; and a lowpass filter coupled to the output of the digital/ analogue converter. The control circuit comprises three bi-stable circuits F1, F2, F3 coupled to form a shift register and three EXCLUSIVE- OR gates Al, A2, A3 with their inputs coupled to respective pairs of outputs from the shift register. Arrival of a first flank produces an output from gate A1 during a first clock pulse ZT which transfers the count of ZA to store SD. During the next clock pulse, gate A2 produces a reset pulse for the counter ZA, which then starts to count subsequent clock pulses until the next plank produces a subsequent output from A1 to transfer the new instantaneous count to the store. During the times that A1, A2 produce outputs A3 also produces an output which prevents the count from being incremented by clock pulses during these intervals. The demodulator is used in an FSK system and a D.C. bias may be superimposed on the output from the D/A converter to produce outputs of opposite polarity corresponding to logical "0" and "1" values of transmitted data.