SU684758A1 - Arrangement for synchronizing by cycles - Google Patents

Description

one

The invention relates to communication technology and can be used in information transmission equipment.

A synchronization device for cycles is known, containing the analyzer connected in series, the first element AND and the counter, as well as the second element AND and the distributor, the output of which is connected to another input of the first element AND, and which is connected to the output of the clock generator 1).

However, this device has a large time to synchronize.

The purpose of the invention is to reduce the time of entry into synchronism.

To do this, the cycle synchronization device containing the analyzer connected in series, the first element AND and the counter, as well as the second element AND and the distributor, the output of which is connected to another input of the first element AND, and the input connected to the output of the clock generator, is connected in series to the first and the second block of the ban, the first divisor, additional1

the counter, as well as the second divider and the third prohibition unit connected in series, the output of which is connected to the input of the counter and the input of the second divider, the second input of which is connected to the output of the clock generator

and the second input of the first divider, the output of which is connected to another input of the second prohibition unit, and the third input of the first divider through the second element I is connected to the output of the first prohibition unit, the output of the additional counter connected to the output of the counter and connected to another input of the distributor whose output is connected to another input of the first block, the other input of which is connected to the output of the analyzer, and the output is connected to the third input of the second divider, another output of which is connected to another input of the second element AND , while the output of the first block of the ban is connected to another input of the third block of the ban, and the output

the second block of the ban is connected to the other input of the additional counter, and the output of the second divider is connected to another input of the counter.

The drawing shows the aruku 1 on the electronic circuit diagram of the uetrons.

A device for scattering but cycles is contained in analyzer 1, elements AND 2. 3, counters, 5, distributor 6, generator 7 1 MPs, dividers 8, 9, prohibition blocks 10-12. The device works as follows. The information encoded by block (p, k) codes enters analyzer 1, at the output of which the following signals appear at a clock frequency: signals 1 when matches and O when the n-bit sequence of the binary sequence of binary symbols does not match the code-building law. These signals are fed to the input element And 2 and to the input of the prohibition unit 10, to the other inputs of KOTOpbix, signals are received corresponding to the -th phase of the distributor 6 (K14p).

If the distributor 6 is phased, then the And 2 element causes the Reset signal, according to which the dividers 8, 9 and counters 4, 5 are reset, and the output of the inhibitor 10 will have no signal. If the distributor 6 is not phased, the signals corresponding to the output of the analyzer 1 pass through the prohibition block 10 and start the divider 8, which begins to divide the clock frequency from the generator 7 to the input of the divider 8 n times.

Through p clocks, divider 8 outputs the first signal to the input of counter 4 and to the input of prohibition block 12, to the input of which signals are received from the output of prohibition block 10, which prohibit (if any) the reset of divider 8 and counter 4.

Thus, if there are correspondence signals on the J. phase of the distributor 6, set by divider 8, the counter 4 counts their number and when a certain threshold is reached, for example, a series of correspondence pulses, it outputs a signal to the input of the distributor 6, phasing it.

. In the absence of confirmation of the signals corresponding to the impulse from the output of the divider 8, passes through the prohibition block 12 and sets the divider 8 and the counter 4 to the initial state. During operation of the divider 8, its output signal to the input of the AND 3 element receives an enable signal delayed by one clock relative to the launch of the divider 8. Therefore, if, in addition to the first correspondence signal, extracted at the J - o phase of the distributor 6, on subsequent phases of the distributor 6 the second signal is selected, it passes through the AND 3 element and starts the divider 9, from the output

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which) zaiuekats sshssik 5, K (counting, reaching i: niiiajii, i ccxniSLMciiiHti and at dps1izhenii obsledlenkogo gk) X) 1a, for example, a series g of correspondence signals, B1 |

impulse to the input of the distributor 6, phasir from go.

In the absence of confirmation of the signals corresponding to the additional channel of the selection. Phase of the signal from the output of the splitter 9 pass;

through block II of the prohibition and sets the divider 9 and 5 to the initial state.

Claims (1)

1. USSR author's certificate N 4987.52, cl. H 04 L 7/08, 1974.