SU729835A1 - Synchronization pulse shaping arrangement - Google Patents

Description

(54) DEVICE FOR THE FORMATION OF A PULSE. SYNCHRONIZATION

I

The present invention relates to the field of IlvmyjTbCHoE technology and can find a name in discrete communication equipment and computing equipment, as well as in equipment quality control. Devices for generating a synchronization pulse are known, comprising a generator, a register circuit, n-counters, 2n-Lopic elements, and a combinational circuit 1. The device is relatively complicated and does not allow to extract a sync pulse relative to any beat sequence.

It is also known a device for generating a synchronization pulse, comprising a main sequence forming unit, which is connected to the output of the clock generator, a counter, a register of the clock number, matching elements, a decoder and a trigger, the first device of which is connected to the output of the decoder, whose inputs are connected to the bit outputs of the meter, and the metering inputs of the meter

connected to the output of the register of the number of the Cysho impulse and through the elements of the scaping, the second inputs of which are combined with each other,

However, in the process of switching the counting device in the specified device at the output of the deosfrarator, the formation of impulses of interference is possible, when switching from one state of the counter to the next, and interference 1g is formed on the same

The output from which the clock pulse is removed. In addition, the output of the decoder, from which the clock pulse is taken, the cutout trigger and the matching elements are connected to the installation methods of the counter,

15 closure of the feedback circuit, which leads to unstable operation of the device.

The purpose of the invention is to increase the stability of the device to the exclusion of the possibility of formation at the exit

th pulses interference.

It is achieved that the inverter, the output of which is connected to

to the second input of the trigger, and the input is connected to the sy by the counting input of the counter and the output of the clock frequency generator. In this case, the combined inputs of the matching elements are connected to the output of the main sequence generating unit.

The drawing shows a block diagram of the proposed device.

It contains the clock frequency generator 1, the main sequence block formation unit 2, the counter 3, the decoder 4, the pulse number register 5, the matching elements 6 - 1 - i 6 - n i D - trigger 7 ,. inverter 8 and clamps 9 and 10.

The device works as follows.

Block 2 converts a sequence of clock pulses from generator 1 into a periodic sequence taken from terminal 10. At the beginning of the period of the main run, an additional output of block 2 forms a goal, revealing the coincidence elements, through which the initial state is written to counter 3 of register 5, corresponding to the selected clock number relative to the beginning of the main sequence period. The number of pulses received from the generator 1 is subtracted from the number 3 of the counter 3, and when the counter receives the number of clock pulses equal to the sync pulse number, the counter assumes the zero state, in which the output of the decoder 4 produces a pulse that pulses are read through T) -r-flip-flop 7 on clamp 9. Pausing is paused by supplying a clock sequence from the generator 1 via the inverter 8 to the synchronization input of the trigger 7.

There are no subtraction counts in the chipboard. The use of the cpc counter is possible when connecting the inverse outputs of register 5 and the setting input of counter 3. In this case, the state corresponding to the clock notaler in the reverse code is written to the counter. A sync pulse is formed at the output of the decoder 4 at a unit in all counts of the counter. This is equivalent to replacing the multi-input circuitry used as a decoder with subtraction scoring

a multi-input matching circuit used as a decoder with an addition counter.

The proposed device does not contain feedback circuits, in contrast to the known ones, and the disturbances that may occur at the output of the decoder 4 do not interfere with the stability of the operation of the device, do not disrupt the synchro pulse formation process and do not affect its duration. The pulse from the output of the decoder counts in a pause between clock pulses. Thus, it is prohibited to block the clock of the sync pulse during the possible appearance of a disturbance pulse caused by switching the counter when the clock invinynbca arrives at its input. A clock pulse formed by the proposed device has a duration of a clock frequency period.

Claims (2)

1. For France of France No. 2283592, class, N OZ K 5 / 2O, 1976. 2. USSR Author's Certificate NO. H 04 H 7 / O2, 1975.