SU1119184A1 - System for transmitting and receiving discrete information - Google Patents

Abstract

1. A DISCRETE INFORMATION TRANSMISSION AND RECEIVING SYSTEM, containing, on the transmitting side, serially connected clock generator, pseudo-random generator, sequences and the first and second modulo-two adders, as well as the synchronizer and transmitter, the first synchronizer input being the information input and the second the input is synchronizing and is connected to the second output of the pseudo-random sequence generator, and on the receiving side - the receiver, the output of which is connected to the first inputs of the first o and the second multipliers, the second inputs of which are connected respectively to the first and second outputs1 01 of the synchronization parameter and reference signal generation unit, the third output of which is connected to the synchronization input of the discrete information separation unit, the information input of which is connected to the output of the first multiplier, which differs from that, in order to ensure noise immunity, a first trigger is inserted into it on the transmitting side, connected between the output of the clock frequency generator and the input of the first adder modulo two, serially connected two-bit shift register and decoder, OR element, four AND elements, second trigger, third modulo-two adder, and gating pulse shaper, the first, second, and third modulo-two outputs and the first output of a pseudo-random sequence generator through the corresponding elements "connected to the corresponding inputs of the OR element, the output of which is connected to the transmitter, the first output of the pseudo-random sequence generator also n It is connected to the first input of the third modulo-two adder, the second output of the pseudo-random sequence generator is connected to the second trigger and two-bit shift register, the information input CO of which is connected to the synchronizer output, and the output of the second trigger X) is connected to the second inputs of the second and third modulators The driver and the driver of the gating pulses are connected to the control input of the decoder, the outputs of which are connected to the second inputs of the corresponding AND elements, and at the receiving side administered adder whose inputs are connected to outputs of the first and second multipliers, and an output connected to an input unit of a preferred sinhroparametra and generating a reference signal at a second multiplier, this output is also

Description

connected to the second information input of the endowment block of discrete information.

2. The system according to claim 1, that is, so that the block of discrete information is implemented in four identical channels, each of which contains a quadratic detector connected in series to the integrator and a block of sample and information storage, the outputs the sampling and storage units and all channels are connected to the information inputs of the deciding unit, the last output of which is the output of the selected discrete information block, and the first output of the modulo two is connected to the second output, the output of which is sequence generator connected to the trigger and strobe pulses npix WMOs .dam connected to the integrators and to the second inputs of the sampling units and storing information of all the channels, to the output of said flip-flop is also connected to the input transducer NOLYarNOSTI to BbKOJDiy

control unit connectors are connected to the unit and the first inputs of the first and second multipliers, the outputs of which are connected respectively to the second inputs of the integrators of the second and third channels, the second inputs of the first and second multipliers are connected respectively to the second inputs of the first and fourth channels integrators and are respectively the first and the second information inputs of the block in the | Purpose of discrete information, and the second input of the modulo two adder is the synchronization input of the block or dis retnoy information.

3. The system of claim 2, so that the block is made in the form of four channels, each of which contains an attenuator, a comparator, and a key, sequentially, and to the outputs of all channel comparators the corresponding inputs of the 1-input element AND, the output of which is the second output of the block of its block, are also connected to the outputs of the keys of the first and fourth channels, respectively, the first and second inputs of the output comparator, to which are also connected via moves the second and third channel key The output yield. The first comparator is the first output of the decision block, the second inputs of the comparator AND key of each channel are combined and the corresponding information input of the deciding unit, the second inputs of the first and second multipliers are combined and are the control input of the decision block, and the inputs of attenuators of the first, second, second and third the fourth channels are connected respectively to the second, first, fourth and third information inputs of the deciding unit.

one

The invention relates to a communication technique, preferably broadband systems, and can be used in radio control.

A well-known broadband system in which correlation devices are used to provide binary information transmitted by means of orthogonal signals, which contain a block for the synchronous parameter and for the formation of reference signals, and a block for information distribution (w lj.

However, the noise immunity of systems using orthogonal signals

Binary information transfer is inadequate in some cases.

The closest technical solution to this invention is a system for transmitting and receiving discrete information containing on the transmitting side serially connected clock oscillator, pseudo-random sequence generator and the first 1 modulo-two adders, as well as the synchronizer and transmitter, the first synchronizer input This is an information input, and the second input is synchronization and coefficients are connected to the second output of the pseudo-random sequence generator, and on the receiving side - n The receiver, the output of which is connected to the first inputs of the first and second multipliers, the second inputs of which are connected respectively to the first and second outputs of the sync parameter and reference signal generation unit, the third output of which is connected to the synchronizing input of the discrete information selection block, information input which is connected to the output of the first multiplier. However, the real noise immunity of such a system for transmitting and receiving discrete information is low. The purpose of the invention is to improve noise immunity. To achieve this goal, the system for transmitting and receiving discrete information, containing on the transmitting side serially connected clock generator, a pseudo-random sequence generator and the first and second modulo-two adders, as well as synchronization and redirector, the first synchronizer input being an information input and the second input is synchronized and connected to the second output of the pseudo-random sequence generator, and on the receiving side a receiver, the output of which is interconnected. to the first inputs of the first and second multipliers, the second inputs of which are connected respectively to the first and second outputs of the block of the synchronization parameter and generating opsphones, the third output of which is connected to the synchronization input of the block of discrete information, the information input of which is connected to the output of the first multiplier, On the transfer side, a first trigger, connected to each other by the output of the clock generator and the input of the first modulo-two adder, connected in series two times a sequential shift register and a decoder, an NL element, four AND elements, a second trigger, a third modulo two adder and a gating pulse shaper, with the outputs of the first, second and third modulo adders two and the first output of a pseudo-random sequence generator connected to the corresponding inputs of the OR element, the output of which is connected to the transmitter, and the first output of the pseudo-random sequence generator is also connected to the first input of the third modulo two , the second output of the pseudo-random sequence of the Yost is connected to the inputs of the second trigger and two-bit shift register, the information input of which is connected to the output of the synchronizer a, and the output of the second trigger is connected to the second inputs of the second and third modulators two and through the pulse shaper of the pulses with the control input of the decoder, the outputs of which are connected to the second inputs of the corresponding elements And, and on the receiving side an adder is entered, the inputs of which are connected to the video The first and second multipliers, and the output are connected to the input of the sync parameter and reference signal generation unit, while the output of the second multiplier is also connected to the second information input of the discrete information extraction unit. The discrete information selection block is implemented in the form of four identical channels, each of which contains a serially connected integrator, a quadratic detector and an information sampling and storage unit, with the outputs of the sampling and information storage blocks of all channels connected to the information inputs of the decision unit, the first output of which is the output of the discrete information block, and the first output is connected to the first input of the modulo two adder, the output of which is connected through a series-connected trigger and forms A strobe pulse is connected to the first inputs of the integrators and to the second inputs of the sample and information storage blocks of all channels. Moreover, the input of the polarity converter is connected to the trigger output, to the output of which the control input of the decision block and the first inputs of the first and second multipliers, the outputs of which are connected, respectively, to the second inputs of the integrators of the second and third channels, the second inputs of the first and second multipliers are connected respectively to the second inputs of the integrators ne The first and fourth channels and are respectively the first and second information inputs of the discrete infrastructure module and the second input of the modulo two is the Synchronization input of the discrete information block. The solver unit is made in the form of four channels, each of which contains an Attenuator, a comparator and a key connected in series, in addition to the outputs of the comparators of all channels, the corresponding inputs of the four-input element I, the output of which is the second output of the soldering unit, are also connected to the outputs of the keys of the first and the fourth channels are connected, respectively, the first and second inputs of the output comparator to which also through the corresponding interceptors. the outputs of the keys of the second and third channels are connected, the output of the output The first comparator is the first output of the resolving unit, the second inputs of the comparator and the key of each channel are combined with the corresponding information input of the resolving unit, the second inputs of the first and second multipliers are combined and are the control input of the decision block, and the inputs of the first attenuators, the second, third and fourth channels are connected respectively to the second, first, fourth and third information inputs of the entire unit. FIG. 1 shows a structural electrical circuit of the transmitting part of the system for transmitting and receiving discrete information / in FIG. 2 - structural electrical reception circuitry. Parts of the system for transmitting and receiving information in}. 3 is a block diagram of a discrete information input unit; FIG. 4 shows the structures on the scheme of the decision block in FIG. 5 and 6 are time diagrams that show how the system works. The device for transmitting and receiving discrete information contains on the transmitting side a clock frequency generator 1, the first trigger 2, the first adder 3 modulo-two, the second adder 4 modulo two, the generator 5 1 4 pseudo-random sequence, the third adder 6 modulo two, the synchronizer 7, a two-bit shift register 8, a decoder 9, a second trigger 10, a gate generator 11, pulse elements OR 12, a transmitter 13, elements 14-14, and on the receiving side a receiver 18, the first multiplier 19, the second multiplier 20, block 21 vi (celein disk emt information, adder 22, block 23 of the sync parameter and the formation of reference signals. Block 21 of the discrete information section contains the first and second multipliers 24 and 25, integrators 26-29, quadratic, detectors, blocks 34-37 of sampling and information storage, solving unit 38 adder 39 modulo two, flip-flop 40, for- and worldizer 41 gating pulses, polarity converter 42. Decision unit 38 contains keys 3-46, multipliers 47-48 output comparator 49, comparators 50-53, attenuators 54-57, four-input element And 58. Transmission system and receiving discrete information works in the following way. The signal of the clock frequency ME (Fig. 5a-5b) from the output of the generator 1 simultaneously posts to the inputs of the first trigger 2 and the generator 5 of a pseudo-random sequence, the inputs of which generate signals U (semiconductor frequency meander) J M (m sequence) and Vf (synchronization signal binary symbols input to the synchronizer input 7). The signal V; j is also fed to the input of the second trigger 10, at the output of which a signal III is generated (a square wave with a period equal to twice the period of binary symbols). As a result of the modulo operations, the two signals M and the outputs of the adders 3, 4, o form three different signals with a period of 2T. In combination with the signal M, they form an ensemble of four orthogonal signals with a peak of 2T (Fig. 5e). The double characters 1 and O, entered at the main input of the synchronizer 7, are recorded with the double shift register 8 at times (times that are multiples of the binary symbol period kT (k 1,2,3, ...). The combination of binary symbols written In the register, at times that are multiples of a double period, the barely-to-be binary 2kT symbols (to 1,2,3, ...) "goes to the decoder 9, which determines the number of the resulting combination and outputs a signal in the form of a potential of a logical unit n to the second input the corresponding element And during the entire time interval (0,2t). As a result, one of the S.-S signals corresponding to a given combination of binary symbols is passed to the input of a radio transmitting device, where the carrier phase is modulated with this signal, the spectrum of the received phase-shifting signal is transferred to the desired frequency range and power gain. As follows from FIGS. 5c-5e, the output signals Sj and Sj of adders and 6 are formed from the signals M and M taken from the outputs of the generator 5 of the pseudo-random sequence and the first modulo-2 adder 2, by means of lnitselnoy inverse manipulation The signal J nalom. Therefore, at the reception stop (Fig. 2) with the forms {{rovag1i) of the reference signals supplied to the second inputs of the first 19 and-second 20 multipliers, it is sufficient to use only these two signals, because regardless of the specific signal variant, if there is a mismatch between the received and the reference signals at the output of the adder 22 buzzts to be present with a half-clock frequency is й or n or fnyl-fS where tnn is a certain intermediate frequency, the amplitude and phase of which are determined by the degree of error. In block 23, the said components are filtered out and behind; As a result of these components either stale or square each of them, inverse manipulation is eliminated and after the filtering of E1, the clock signal M is used, which is used to synchronize the reference signals. Thanks to the multipliers 24 and 25, in block 21 of the formation specific to them (Fig. 3), 1 48 additional inverse manipulation of the output signals of the multipliers 19, MEjT b form and 20 signals in the converter code displayed on the polarity 42 from the output signal J trigger 40 is carried out. Suppose that in the interval (0.2T) a signal S was transmitted. Then, with cyclic synchronization as a result of correlation processing, the input mixture consisting of the wanted signal S (t) and noise n (t) y (t) S (t) (t) 0 t $ 2T at the outputs of the channels (taking into account the delay by 2T) stresses / (l., representing the cross-correlation products between y (t) and the corresponding reference signals (Fig. 6a)) appear. These voltages are applied to the information inputs of the decision block 38 ( Fig. 4) and further - to the switched inputs of the keys 43-46 and to the non-inverting inputs of the shaps 50-53. The inverting inputs of the comparators are received aprons from the outputs of the corresponding attenuators 54-57. The sign of the difference between these voltages (fig. 6d) determines the state of the corresponding keys 43-46. With a positive sign, the potential of the comparator appears at the output of the comparator, and if negative, the logical zero. , the key, at the control input of which a potential unit appears, is open, and j the output voltage of this channel is fed to the corresponding input of the output comparator 49 either directly or through the corresponding multiplier 47, 48. Latter are needed for the final deciding the received signal and for decoding the received information, i.e., to restore the original sequence of military symbols. Consequently, at the output of the output to the sharathor 49 (radio output), an immediately transmitted sequence of binary symbols is formed in the time scale (Fig. 6c). This is achieved in the following way. Since in the processing channels one hundred tons of square-law detectors 30-33, then

the output voltages of the channels can only be positive, which is reflected in fig. 6a. The output voltage of the first channel U through the switch 43 is applied to the non-inverting input of the output comparator 49, and the output voltage of the third channel Uj is multiplied at the beginning in the multiplier 48 by a signal (Fig. 5i) and then fed to the inverting input of the output comparator 49. The sign of the difference these voltages at each time interval (O, T) and (T, 2T) (Fig. 66) determine the output level of the output comparator (Fig. 6c). . At the same time, at the output of the four-input element And 58 (at the correction output of the decision block 38) there will be 20 potential of a logical zero, since at the outputs of the comparators 51 and 53, according to FIG. 6g, there will be zero potentials. . In the absence of cyclic synchronization-25 zafi, i.e. with a time shift between the received and reference signals equal to T, the situation arises,

when the voltage at the outputs of the channels. about the same. This is always the case when different signals are transmitted on two adjacent intervals of 2T duration (Fig. 5e). Then, the high potentials of logical units appear at the outputs of all comparators 50-53, which leads to the appearance of the potential of the logical unit at the corrective output of the decision block 38. The potential of the logical unit 1 1 at the second input of the modulo-two adder is equivalent to the BAN signal for passing synchronizing pulses U, (fig. 5g) to the input of the trigger 40, determining the temporal position of the gating pulses V (fig. 5h). As a result, a strobe pulse is delayed by one period of the clock pulse, i.e. for the time T, which leads to the restoration of the frame synchronization and to the correct decoding of the received information | 1 and in the decision block 38. Thus, as a result of the use of the invention, the noise immunity is increased.

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Claims (3)

1. A SYSTEM FOR TRANSMITTING AND RECEIVING DISCRETE INFORMATION, comprising, on the transmitting side, a series-connected clock generator, a pseudo-random generator. sequences and the first and second adders are modulo two, as well as a synchronizer and a transmitter, the first input of the synchronizer being an information input and the second input being synchronizing and connected to the second output of the pseudo-random sequence generator, and on the receiving side, a receiver whose output is connected to the first the inputs of the first and second multipliers, the second inputs of which are connected respectively with the first and second outputs of the block selection of the sync parameter and the formation of reference signals, the third output for which it is connected to the synchronizing input of the discrete information extraction unit, the information input of which is connected to the output of the first multiplier, which differs from the fact that, in order to increase noise immunity, the first trigger is inserted on it on the transmitting side, connected between the output of the clock generator and the input of the first adder modulo two, sequentially connected two-bit shift register and decoder, element OR, four elements And, the second trigger, the third adder modulo two and the gate generator pulses, and the outputs of the first, second and third adders modulo two and the first output of the pseudo-random sequence generator through the corresponding AND elements are connected to the corresponding inputs of the * OR element, the output of which is connected to the transmitter, and the first output of the pseudo-random sequence generator is also connected to the first the input of the third adder is modulo two, the second output of the pseudo-random sequence generator is connected to the inputs of the second trigger and a two-bit shift register, in the formation input of which is connected to the output of the synchronizer, the output of the second trigger connected to the second inputs of the second and third adders modulo two and through the gate pulse generator is connected to the control input of the decoder, the outputs of which are connected to the second inputs of the corresponding elements And, and on the receiving side the adder , the inputs of which are connected to the outputs of the first AND second multipliers, and the output is connected to the input of the block selection of the sync parameter and the formation of reference signals, while the output The second multiplier also 1112184 is connected to the second information ¹ input of the discrete information injection unit, 2. The system according to claim 1, with the fact that the discrete information extraction unit is made in the form of four identical channels, each of which contains a quadratic detector and an information sampling and storage unit connected in series _f moreover, the outputs of the blocks of sampling and storing information of all channels are connected to the information inputs of the decision block, the first output of which is the output of the discrete information allocation unit, and the first input of the adder modulo two is connected to the second output, the output of which is via consequently, the connected trigger and the gate driver * is connected to the first inputs of the integrators and to the second inputs of the blocks for selecting and storing information of all channels, and the output of the polarity converter is also connected to the output of the trigger, to the output of which the control input of the decision block and the first inputs of the first and the second multipliers, the outputs of which are connected respectively to the second inputs of the integrators of the second and third channels; the second inputs of the first and second multipliers are connected respectively to the second inputs of the integrators of the first and fourth channels and are respectively the first and second information inputs of the discrete information allocation unit, and the second adder input modulo two is the / synchronizing input of the discrete information extraction unit. 3. The system according to claim 2, characterized in that the decision unit is made in the form of four channels, each of which contains sequentially connected attenuator, compara _; .tor and key, and the corresponding inputs of the four-input element And, the output of which is the second output of the deciding unit, are also connected to the outputs of the comparators of all channels, the first and second inputs of the output comparator are connected respectively to the outputs of the keys of the first and fourth channels, to which are also connected via corresponding multipliers the outputs of the keys of the second and third channels, the output of the output comparator is the first output of the decisive block, the second inputs of the comparator And the key of each channel are combined and are Xia respective data input deciding unit, the second inputs of the first and second multipliers are combined and the control input of the decision block, the inputs of attenuators first, second, third and fourth channels are connected respectively to the second, first, fourth and third data inputs of the block casting. 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