SU1506561A1 - Device for receiving batched data in satellite communication system - Google Patents

Abstract

The invention relates to radio engineering and communications. The purpose of the invention is to improve the noise immunity of receiving packet information. To achieve the goal, a device containing demodulator 1, a synchronization signal detector 2, a synchronization unit 3, an aperture signal generator 4, a demultiplexer 5, a terminal equipment block 6, two blocks 7, 8 of memory, two blocks 9, 10 write addresses, two delay elements 11, 12, an inverter 13, an element OR 14, a block 15 of read addresses, two keys 16, 17, two multipliers 18, 19, two integrators 20, 21, and a block 22 of comparison. Information is read from blocks 7 and 8 with a delay relative to the start of the recording for a time equal to the packet length Τ _N. The delay is provided by the synchronization of the block 15 by the delayed element of the delay 11 by Τ _N signal from the output of the element OR 14. By the clock, the block 15 is synchronized by the system clock signals that do not have clock edge inhomogeneities. Since the recording is controlled in one block of memory by clock signals with a direct phase, and in another with an inverse, in one of the recording options it will be produced with the best conditions from the point of view of phase relations. 1 il.

Description

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3150656

1st hardware, two blocks 7, 8 of memory, two blocks 9, 10 write addresses, two delay elements 11, 12, inverter 13, element OR 14, block 15 5 read addresses, two keys 16, 17, two multipliers 18, 19, two integrators 20, 21 and a unit 22 of the comparison. The reading of information from blocks 7 and 8 is delayed relative to the beginning by a time equal to the packet length G. The delay is provided by the synchronization of block 15

delayed delay element 11 by in signal from the output of the element OR 1A. In cycles, block 15 is synchronized with system clock signals that do not have clock edge inhomogeneities. Since the recording is controlled in one block of memory by clock signals with a direct phase, and in another with an inverse, in one of the variants the recording will be made with the best conditions from the point of view of phase relations. 1 il.

The invention relates to radio engineering and communication, and can be used in a radio communication system with multiple access and time multiplexing of signals from various stations in a transponder trunk, in particular in a satellite communication system.

The purpose of the invention is to increase the noise immunity of receiving packet information.

The drawing shows a device for receiving packet information of a satellite communication system.

The device contains demodulator 1, detector 2 of synchronization signals, synchronization unit 3, generator of aperture signals 4, demultiplexer 5, blocks 6 of terminal equipment, first and second blocks 7 and 8 of memory, first and second blocks 9 and 10 write destinations, the first and second delay elements 11 and 12, the inverter 13, the OR element 14, the read address block 15, the first and second keys 16 and 17, the first and second multipliers 18 and 19, the first and second integrators 20 and 21, block 22 comparison.

A device for receiving packet information of a satellite communication system operates as follows.

The intermediate frequency signal is fed to the input of demodulator 1, which decodes the signals and generates the accompanying packet clock sequence. At 4-phase relative phase shift keying, two information channels are formed at the output of demodulator 1. The signals from the output of demodulator 1 are fed to the detector 2 of the synchronization signals, which performs processing using the aperture signal of the master and peripheral sync packets.

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earth stations. The detected synchronization signals enter block 3 and are used as reference for the phase locked loop of its frequency. Block 3 generated continuous and system-stable clock signals

5 are provided to a demultiplexer 5 and an aperture shaper 4, which is synchronized in cycles by detector 2 and produces gating signals used for temporal selection of sync packets.

The clock signals from the output of the demodulator 1 are fed to the first and second multipliers 18 and 19, the second inputs of which are supplied with continuous forward and inverse system clock signals from block 3 and inverter 13, respectively. The outputs of the first and second multipliers 18 and 19 are connected respectively to the first second integrators 20 and 21, which integrate the multiplication result over a time interval equal to the length of the received packet. This interval is defined as the sum of the time separated signals.

5 apertures formed by demultiplex. By the connection 5, connected by the element OR 14. Each of the aperture signals corresponds to the time position of the information packets in the loop of one of the transmitted digital streams and is determined by the schedule of communications currently in effect. The aperture signals are multiplexed by the multiplexer 5 using signals

5. Cycle and clock signals generated by the detector 2 and block 3, respectively.

The signals from the outputs of the first and second integrators 20 and 21 arrive at

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comparison unit 22, which compares two input signals by levels, if, for example, the signal from the output of the first integrator 20 is greater than the signal from the output of the second integrator 21, then logical 1 is set at the first output of block 22, and logical Oh and vice versa.

Due to the fact that the information signal from packet to packet fluctuates in phase within the guard interval between packets and the instantaneous phase value of the signals of the master oscillators for transmission of other earth stations differ from each other, demodulator 1 generates clock signals, the phase of which varies from packet to the packet with respect to the clock signals generated by block 3. Information signals from the output of demodulator 1 are received in parallel to the inputs of the first and second blocks 7 and 8, controlled by the recording of the first and second blocks 9 and 10. The first and second blocks 9 and 10 are synchronized on a cycle by a signal from the output of the element OR 14, and on clocks - by direct and inverse clocks from the output of block 3 and the inverter 13. Read information from the first and second blocks 7 and 8 is carried out with a delay relative to the start of recording for a time equal to the packet length. The delay is provided by the synchronization of the block 15 by the delayed first delay element 11 on the C signal from the output of the element OR 14. By the clock, the block 15 is synchronized by the system clock signals that do not have non-uniform. Clock edges. The reading is performed simultaneously from the first and second blocks 7 and B.

The state of block 22 determines the first or second block 7 or 8 of the memory.

when recording in which clock phase

The signal turned out to be optimal with respect to the phase of the received information signal. Since the recording is controlled in one block of memory by clock signals with the direct phase, and in the other with inverse, in one of the options, the recording is performed with the best conditions from the point of view of phase relations. These best conditions will be found in the memory block in which the output signal of the first or second multipliers 18 and 19 is higher.

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The integragamy signal is multiplied by the first and second intografts 20 and

21 excludes the effect of phase noo-similarities in clock signals. Block

22 through the first and second keys 16 and 17 connects the output of the first or second blocks 7 or 8 to the information inputs of the demultiplexer 5.

Claims (1)

The cycle signal is supplied from the demultiplexer 5 to the input of blocks 6 with a delay on which the second delay element 12 provides. The demultiplexer 5 commutes temporary information packets. The decultiplexer 5 also generates time windows for each block 6, which allocate information packets forming one direction of communication. Invention Formula The device for receiving packet information of the satellite communication system, contains a demodulator, the first and second information outputs and the clock output of which are connected respectively to the first, second and third inputs of the synchronization signal detector, the first output of which is connected to the synchronization unit, the output of which is connected to the first input of the driver signals of the aperture and the clock input of the demultiplexer, each group of outputs of the demultiplexer consisting of the first and second information outputs, the clock output, The output of the aperture signals and the cycle signal outputs is connected to the inputs of the corresponding terminal equipment unit, while the output of the aperture signal generator is connected to the fourth input of the synchronization signal detector, the second output of which is connected to the second input of the aperture signal generator, which is designed to improve noise immunity receiving packet information, the first and second blocks of memory are entered, the first and second blocks of write addresses, the first and second keys, the first multiplications connected in series and the integrator, the second multiplier and the integrator, the comparison unit, the inverter, the read address block, the first and second delay elements, and the OR element, the first and second information outputs of the demodulator are connected in series with the first and second inputs of the first and second memory blocks, the first output of the first memory block is connected to the first input of the first key, the output of which is connected to the first information input of the demultiplexer, the second output of the first memory block is connected to the first input of the second key, the output of which connected to the second information input of the demultiplexer, the outputs of the aperture signals of each group of outputs of which are connected to the corresponding inputs of the OR element, the output of which is connected to the first inputs of the first and second blocks address The first and second inputs of the first and second integrators and the input of the first delay element, the output of which is connected to the first input of the block of readout addresses, the output of which is connected to the third inputs of the first and second memory blocks, are connected to the first and second outputs of the second memory block. with the second inputs of the first and second keys, while so The demodulator output is connected to the first inputs of the first and second multipliers, the outputs of the first and second integrators are connected respectively to the first and second inputs of the comparison unit, the first output of which is connected to the third inputs of the first and second switches, the second output of the comparison unit is connected to the fourth input 1 and the first and the second one, the output of the synchronization unit is connected to the input of the inverter and the second inputs of the first multiplier, the block of read addresses and the first block of write addresses, the output of which is connected to four the inlet of the first memory block, the inverter output is connected to the second inputs of the second multiplier and the second block of write addresses, the output of which is connected to the fourth input of the second memory block; the third output of the synchronization signal detector is connected to the input of the second delay element whose output is connected to the input of signals demultiplexer loop.