SU1555892A1 - Device for synchronizing code sequence - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve the accuracy of the phase correction signal of the clock frequency when receiving a bi-pulse relative signal. The clock synchronization device contains a master oscillator 1, a time selector 2, a front selection block 3, a phase discriminator 4, an add-subtract block 5, a frequency divider 6, a trigger 7, a modulator two 8, a shift register 9, a HE element 10 and the AND element - NOT 11. If the bi-pulse relative signal undergoes large temporal distortions as it passes through the communication line, then a signal with large edge distortions arrives at the input of the device. In the clock synchronization device, the double clock frequency is adjusted to the edges of the received signal and the clock frequency gates are generated from one of the phases, which leads to the elimination of errors when decoding the bi-pulse relative signal. 1 il.

Description

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The invention relates to a telecommunication technique and can be used to extract a clock frequency from a received bi-pulse relative signal, as well as in the construction of receiving devices included in the device for converting signals operating on symmetrical metal pairs.

The aim of the invention is to improve the accuracy of the phase correction of the clock signal when receiving a bi-pulse relative signal with a large level of temporal distortion.

The drawing shows a structural electrical circuit of a clock synchronization device.

The clock synchronization device contains a master oscillator 1, a time selector 2, a front edge selection block 3, a phase discriminator 4, an add-subtract block 5, a frequency divider 6, a trigger 7, a modulator two 8, a shift register 9, a HE element 10, an AND element -NOT P.

The clock synchronization device operates as follows.

The pulses from master oscillator 1 are fed to block 5 and then to divider 6 with a common division factor. The outputs of divider 6 generate pulse sequences at twice the clock frequency and clock frequency with a repetition period T / 2 and T, and the recovered clock signal is obtained by dividing by two doubled clock frequency, in-phase with the fronts of the received bi-pulse relative signal. The recovered clock signal is applied to modulator two modulator 8, and the double clock signal is fed to phase discriminator 4

The input relative bi-pulse signal enters the time selector 2, where the input signal is estimated by its duration, the pulses of the master oscillator 1 are used as time marks

In block 3, the leading and trailing edges of the received signal are formed. The selection of fronts is carried out by adding modulo two two information sequences shifted by a period of high frequency. With block 3, the generated front pulses are fed to the phase discriminator 4 and to the AND-NAND 11 element.

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In phase discriminator 4, the moment of arrival of a front pulse from block 3 and the moment of arrival of a pulse from the output of divider 6 are compared. Depending on the phase shift, the error signal is generated in the form of advance or backward pulses. The advancing and lagging pulses from the outputs of phase discriminator 4 are fed to the inputs of block 5, to which the pulse sequence is also fed from the master oscillator 1. In block 5, if there are no pulses to lead and lagging 1, the input frequency is divided by two, while the output of block 5 forms a pulse sequence pulses with a duty cycle of four.

When a pulse arrives at block 5, the backlog of the output signal remains in the state of logical 1 for a period of high frequency, and the phase of the output pulse sequence shifts to the right by a period of high frequency. As a result, at the output of the divider 6, the clock frequency phase is shifted in the direction of advance.

When a pulse, Advance 1, arrives at block 5, the output signal remains in the state of logic O for a high frequency period, and the Phase of the output pulse sequence is shifted to the left by a period of high frequency. As a result, at the output of the divider 6, the clock phase often shifts towards lagging.

Thus, the clock frequency clock is tuned to the fronts of the input information.

The adjusted clock signal from the output of the divider 6 is fed to the input of the modulo two 8 and from its output to the device output.

When receiving a BIO signal with small time distortions, the gating edge of the output clock frequency is located in the middle of the received BIO signal, regardless of the initial phase, while the decoding quality of the BIO signal into the information signal is also independent of the initial phase of the clock frequency.

In the case when the BIO signal undergoes large temporal distortions when passing through the communication line, a signal with large edge distortions arrives at the input of the device. By mouth

Clock synchronization occurs. Adjustment of the double clock frequency to the edges of the received signal and the formation of clock frequency gating pulses from one of the phases. To set the clock signal to one of the states using shift register 9, the clock signal is shifted using a pulse sequence from the third clock output of the frequency divider 6, inverting the shifted sequence on the HE element 10, which is fed to the input of the NAND element 11, the inputs of which also receive the output signal of the clock frequency and the front pulse from block 3, and a pulse is generated at the output of the element NE-11, which arrives at the input of the trigger 7, sweeps f igger in the opposite state. The trigger signal 7, modulo-two, arrives at the input of the adder 8, changes the phase of the clock output at its output to the opposite, while the gating edge of the clock output signal is located in the middle of the wide send of the distorted BIO signal, which leads to the elimination errors when decoding.

Thus, the clock synchronization device allows to correct the phase of the selected clock frequency at large levels of temporal distortions of the received bi-pulsed relative signal and, therefore, allows to eliminate errors during

transmission range or increased operating speed.

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Claims (1)

The invention of a clock synchronization device comprising a master oscillator and a time selector connected in series, a frontalization unit, a phase discriminator, an addition and subtractor and a frequency divider whose first clock output is connected to the clock input of the phase discriminator, the first input of the time selector is an input device, the output of the master oscillator is connected to the combined second inputs of the time selector, the edge selection block n the addition and subtraction block, the output times The selector is the first output of the device, characterized in that, in order to improve the accuracy of the phase correction of the clock signal when receiving a bi-pulse relative signal, serially connected modulo two, the shift register, the element HE, the NAND element and the trigger, are entered. which is connected to the signal input of the modulo two adder, the clock inputs of the modulo two adder and the shift register are the second and third outputs of the frequency divider, 5, the information input of the shift register combined with the second input element-1 and AND-NOT is the output of the device, the third input of the element AND-NOT is connected to the output of the front selection block decoding a BIO signal at up to 40