SU1277411A1 - Clocking device for discrete information receiver - Google Patents

Abstract

The invention relates to telecommunications and provides for improved synchronization accuracy. The device contains ADC 1, shift registers 2, 8, 9, p-channel block 3 multipliers (CU), input adder (BC) 4, error signal generator 5, scaling unit 6, n signal processing circuits 7, additional multiplier 10 and 11, subtractor 12, accumulating adder 13, frequency divider 14, correction unit 15 and master oscillator 16. PC 2, BU 3, Sun 4, error signal generator 5, scaling unit 6 and n signal processing circuits form a correction unit and corrects the intersymbol distortion of the input signal. The multipliers of the CU 3 perform the functions of attenuators, changing the level and sign of the signals fed to the aircraft 4. Through the multipliers of the CI 3, the sun 4 receives correction signals resulting from the addition of which correlates the intersymbol distortions of the input information signal to the main signal. 1 3.p. f-ly, 2 ill. , ff 1

Description

The invention relates to telecommunications and can be used for clock synchronization of receivers of discrete information of data transmission systems.

The purpose of the invention is to improve the synchronization accuracy.

Figure 1 shows the structural electrical circuit of the device. Tactical synchronization of the receiver of discrete information; Fig. 2 shows diagrams of the impulse response of the communication channel at the optimal position of the samples (Fig. 2c) and with the readings shifted, respectively, in the direction of advance and lag (Fig. 2S, &),

The device's clock synchronization of the discrete information contains an analog-to-digital conversion, a teler (ADC) 1, the first register 2 of the shift (adaptive) correction,

ha, n-channel block 3 multipliers.

The multipliers of the n-channel block 3 multipliers in the input adder 4 receive correction signals, as a result of the addition of which and the main 25 signal, the intersymbol distortions of the input information signal are corrected,

input adder 4, error signal generator 5, scaling unit 6, n signal processing circuits 7, first and second additional shift registers 8 and 9, first and second additional multipliers 10 and 11, subtractor 12, accumulator / frequency accumulator 13, frequency divider 14 , the correction unit 15 and the master oscillator 16, the n signal processing circuits 7 contain multipliers 17, adders 18 and shift registers 19.

The device clock synchronization receiver of discrete information works as follows.

The input information (analog) signal in the 0-f frequency band is fed to the A / D converter 1 (Fig. 1), in which the instantaneous values (samples) of this signal with a frequency of 2F 4f (main and additional samples) are sampled. Counts in ADC 1 are converted to multi-bit numbers in binary code,

From the output of the A / D converter, 1 numbers with a frequency of .2F are fed to the input shift register 2, which has 2p bits and n taps from them. The input register 2 dvd and ha, as well as the n-channel block 3 multipliers, the input adder 4, the error signal generator 5, the scaling unit 6 and the signal processing circuits, constituted the correction node, corrects the intersymbol distortion of the input signal. The taps of the input register 2 shift through the n-channel unit 3 multipliers are connected to the inputs of the 1 input adder 4.

The multipliers of the n-channel block 3 multipliers perform the functions of attenuators, changing the level and sign of the signals fed to the input adder 4. The transfer coefficient of each multiplier of the n-channel block 3 multipliers is determined by the size and sign of the signals (coefficients) fed to the second inputs of n -channel

block 3 multipliers. The transfer coefficient of one of the multipliers of the n-channel block 3 multipliers (average) is close to 1 and is the transfer coefficient of the central tap,

Through it enters the input adder 4 main signal. The remaining multipliers of the n-channel block of 3 multipliers have transmission coefficients less than 1, which are modified by the auto-multiplier process of the n-channel block of 3 multipliers, and input correction 4 receives correction signals, as a result of which and the main signal are added, the intersymbol distortion correction occurs. input information signal

In the error signal generator 5, an error signal e (c) is generated, which is determined from the expression

e (c,) f (t) -f (t),

where f (t) is a signal with linear distortion;

f (t) is the signal recovered from f (t) without distortion (with approximation). Dp forming the multiplier transfer factors of the n-channel block 3 multipliers, the error signal e (t) is multiplied with the sign signal of each tap of the input register 1 in multipliers 17, as a result of which control signals are generated in the form of a constant component, the value of which is proportional to the values

impulse response u

and „, and.

U-f, (fig. 2a, (, b).

From the outputs of the multipliers 17, the control signals arrive at the inputs of the sum-, tori 18, which, together with the shift registers 19 connected to their outputs, perform the functions of accumulating adders, average signals from the multipliers 17 and store them, From the outputs of the shift registers 19 the signals of the coefficients the transmissions are fed to multipliers of the n-channel block 3 multipliers and change the data transmitted from the tapes of the input register 2

312

shifting the signals in such a way that the output of the adder 4 is reduced distortion. The process of correcting distortion occurs automatically and continuously until the distortion is suppressed. In this case, at the outputs of the multipliers 17, the average value of the signals becomes close to zero, and the changes in the transfer coefficients of the multipliers of the n-channel unit 3 multipliers are terminated.

The timing of signal gating in the A / D converter 1 is carried out in the process of automatically correcting the distortion of the input signal.

The difference between the counts of the impulse response (Fig. 2a, 5,6) uU,.., And the values of U, and U are obtained as the signal of the phase error of the clock pulses, by correlating the signal of the sign of the main samples with the amplitude and the sign of additional counts

.K.,

-.45V ..- where and ,, U3 ... U2, -additional

input readouts 30

this signal; h

and, and . .and signs of the main

counts. To obtain the signal & U from the output of the input adder 4, the signal of axial and additional samples is fed to the first and second successively connected additional registers 8 and 9 of the shift, in each of which the digital signal delays by one clock frequency interval 2F, as a result which results in three digital signals that differ by a shift in time by. From the digital signal from the outputs of the first additional shift register 8, only a sign bit is taken and fed to the second inputs of the first and second additional multipliers.

10 and 11. At the first inputs of the latter, multi-digit numbers are supplied, and the inputs of the first additional multiplier 10 are lagging, and the input of the second additional multiplier

11 - leading relative to the sign. In the first and second additional multipliers, the numbers of the digital signal are multiplied with the sign signal.

Q

five

0

0 5

0

five

moreover, at their outputs, signals are generated corresponding to the products "and and and and

2 to 2k 2K-1

From the OUTPUTS of the first and second additional multipliers 10 and 11, the numbers with a frequency of 2F are fed to the subtractor 12, in which the difference of each pair of input numbers is determined. From the output of the subtractor 12, the digital signal is fed to an accumulating adder 13, in which the average value of the incoming numbers, proportional to MJ, is converted to a frequency by periodically overflowing it. Accumulating adder 13 is clocked by a clock signal with a frequency F, while

tT

the sync signal extracts from input numbers only those derived from multiplying with the sign of the basic samples. When the accumulating adder 13 overflows, an overflow signal (pulse) and a sign signal of the input numbers causing it overflow are formed, the frequency of the overflow signal is proportional to the value, and the sign corresponds to

,

The pulses and the overflow sign signal are fed to a correction block 15, which performs the functions of adding or excluding pulses from the pulse train from the master oscillator 16. In the frequency divider 14, pulse sequences with frequencies F and 2F are formed from the signal divider 14, the first of which is supplied as a clock signal to the accumulating adder 13 and the shift registers 19, and the second after. The value of the impulses with a frequency of 2F is in the ADC 1, the first and second additional registers 8 and 9 of the shift and in the input register 2 of the shift.

The joint process of automatic correction and adjustment of the clock samples of the signal is carried out as follows.

At the initial moment, the samples obtained randomly in ADC 1 (FIG. 25, b) enter through the correction unit to the clock sample adjustment unit, which includes the first and second additional shift registers 8 and 9, the first and second additional multipliers 10 and 11, subtractor 12, accumulating adder 13, frequency divider 14, correction unit 15, master oscillator 16. The clock sample adjustment node analyzes the input signal using additional samples and works out the position of the samples in such a way that the difference of the impulse response values in during the correction node has become zero, i.e. di 0, and the correction node does not have time to change, the signal, since it is tuned slower than the clock adjustment node. Further, the correction node begins to change (correct) the signal, as a result of which the value of uU changes and again the clock adjustment node changes the position of the samples. The process of joint adjustment of the correction unit and the clock adjustment unit continues until the impulse response of the signal path becomes sinu) (Fig. 2a), after which the adjustment process is terminated because the control signals of the correction unit, U.-U and The clock adjustment node is set to zero.

Thus, due to the fact that the main and additional samples of the input signal are corrected in the process of adjusting their temporal location, and additional samples are used for adjusting them that do not affect the operation of the correction unit, the position of the samples is set optimally with different linear distortions of the input signal :

Claims (2)

The invention relates to telecommunications and can be used for clock synchronization of receivers of discrete information of data transmission systems. The purpose of the invention is to improve the synchronization accuracy. Figure 1 shows the structural electrical circuit of the device. Tactical synchronization of the receiver of discrete information; Fig. 2 shows diagrams of the impulse response of the communication channel at the optimal position of the samples (Fig. 2c) and with the readings shifted, respectively, in the direction of advance and lag (Fig. 2S, &), the receiver's clock synchronization device. The discrete information contains analog-digital transform, tel (ADC) 1, first shift register 2, n-channel block 3 multipliers. input adder 4, error signal generator 5, scaling unit 6, n signal processing circuits 7, first and second additional shift registers 8 and 9, first and second additional multipliers 10 and 11, subtractor 12, accumulator / frequency accumulator 13, frequency divider 14 , the correction unit 15 and the master oscillator 16, n signal processing circuits 7 contain multipliers 17, adders 18 and shift registers 19. The device clock synchronization receiver of discrete information works as follows. The input information (analog) signal in the 0-f frequency band is fed to the A / D converter 1 (Fig. 1), in which the instantaneous values (samples) of this signal with a frequency of 2F 4f (main and additional samples) are sampled. The readings in ADC 1 are converted into multi-digit numbers in binary code. From the output of ADC 1, numbers with a frequency of .2F are sent to the input shift register 2, which has 2n bits and n taps from them. Input register 2 as well as the n-channel block 3 multipliers, the input adder 4, the error signal generator 5, the scaling unit 6 and the signal processing circuits constituting the correction node, perform the intersymbol distortion correction of the input signal. The taps of the input register 2 shift through the n-channel unit 3 multipliers are connected to the inputs of the input adder 4. The multipliers of the n-channel unit 3 multipliers serve as attenuators, changing the level and sign of the signals fed to the input adder 4. The transfer coefficient of each multiplier n is channel block 3 multipliers is determined by the magnitude and sign of the signals (coefficients) supplied to the second inputs of the n-channel block 3 multipliers. The transfer coefficient of one of the multipliers of the n-channel block 3 multipliers (average) is close to 1 and is the transfer coefficient of the central tap. Through it, the main signal is fed into the input adder 4. The remaining multipliers of the n-channel block 3 multipliers have transmission coefficients less than 1, which are changed during the automatic (adaptive) correction. Through multipliers of the n-channel block 3 multipliers, the correction signals are received in the input adder 4, as a result of which the main signal is added correction of intersymbol distortions of the input information signal; In the error signal generator 5, an error signal e (c) is generated, which is determined from the expression e (c,) f (t) -f (t), where f (t) is a signal with linear distortions mi; f (t) is the signal recovered from f (t) without distortion (with approximation). Dp of generating multipliers transfer factors of an n-channel block of 3 multipliers, the error signal e (t) is multiplied with the sign signal of each tap of input register 1 in multipliers 17, as a result of which control signals are generated in the form of a constant component whose value is proportional to the pulse value reactions U and „, and. Uf, (FIG. 2a, (b).) From the outputs of the multipliers 17, the control signals are fed to the inputs of the sum-, tori 18, which, together with the shift registers 19 connected to their outputs, perform the functions of accumulating adders, average signals from the multipliers 17 and storing them. From the outputs of shift registers 19, the signals of transmission coefficients are fed to multipliers of the n-channel block 3 multipliers and change the signals transmitted from the taps of the input register 2 3 to shift in such a way that the distortion at the output of the input adder 4 is reduced. It occurs automatically and continuously until the distortion is suppressed. At the outputs of the multipliers 17, the average value of the signals becomes close to zero, and the transmission coefficients of the multipliers of the n-channel block 3 multipliers stop changing.The adjustment by gates of the signal in the ADC 1 is performed during the automatic process correction of input signal distortion. As the phase error signal of the clock pulse phase, the difference in counts of the impulse response is used (Fig. 2a, 5.6) uU,. ,, whereby the values of U and U are obtained by correlating the signal of the sign of the main samples with the amplitude and the sign of the additional samples .K., -.45V ..- where and, U3. ..U2, -additional readings of the input information signal; and, and . .i are the signs of the main sample counts. To obtain the signal & U from the output of the input adder 4, the signal of axial and additional samples is connected to the first and second additional shift registers 8 and 9, each of which delays the digital signal by one clock interval of 2F, as a result which results in three digital signals that differ by a shift in time by. From the digital signal from the outputs of the first additional register of the 8th shift, only a sign bit is taken and fed to the second inputs of the first and second additional multipliers 10 and 11. The first inputs of the latter are supplied with multi-digit numbers, and the inputs of the first additional multiplier 10 are lagging and at the input of the second additional multiplier 11, leading with respect to the sign In the first and second additional mind of the knives, the numbers of the digital signal are multiplied with the sign signal. moreover, at their outputs, signals are generated corresponding to products „and and and and 2 to 2k 2K-1 C of the OUTPUTS of the first and second additional multipliers 10 and 11 numbers with a frequency of 2F enter the subtractor 12, which determines the difference of each pair of input numbers . From the output of the subtractor 12, the digital signal is fed to an accumulating adder 13, in which the average value of the incoming numbers, proportional to MJ, is converted to a frequency by periodically overflowing it. The accumulating adder 13 is clocked by a clock signal with a frequency F, while the clock signal extracts from the input numbers only those that are obtained from multiplying with the sign of the main samples. When the accumulating accumulator 13 overflows, an overflow signal (pulse) and a sign signal of the input numbers causing it overflow are formed, the frequency of the overflow signal is proportional to the value, and the sign corresponds to the sign. The pulses and the overflow sign signal are applied to the add-on or exclusion function pulses from a sequence of pulses coming from the master oscillator 16. In the frequency divider 14, a sequence is generated from the signal coming from the correction unit 15 These pulses are with frequencies F and 2F, the first of which is supplied as a sync signal to accumulating adder 13 and shift registers 19, and the second after. The value of the impulses with a frequency of 2F is in the ADC 1, the first and second additional registers 8 and 9 of the shift and in the input register 2 of the shift. The joint process of automatic correction and adjustment of the clock samples of the signal is carried out as follows. At the initial moment, the samples obtained randomly in ADC 1 (FIG. 25, b) enter through the correction unit to the clock sample adjustment unit, which includes the first and second additional shift registers 8 and 9, the first and second additional multipliers 10 and 11, subtractor 12, accumulating adder 13, frequency divider 14, correction unit 15, master oscillator 16. The clock sample adjustment node analyzes the input signal using additional samples and works out the position of the samples in such a way that the difference of the impulse response values in during the correction node has become zero, i.e. di 0, and the correction node does not have time to change, the signal, since it is tuned slower than the clock adjustment node. Further, the correction node begins to change (correct) the signal, as a result of which the value of uU changes and again the clock adjustment node changes the position of the samples. The process of joint adjustment of the correction unit and the clock adjustment unit continues until the impulse response of the signal path becomes sinu) (Fig. 2a), after which the adjustment process stops because the control signals of the correction unit, U.-U and the node for adjusting the clock counts are set to zero. Thus, due to the fact that the main and additional samples of the input signal are corrected in the process of adjusting their temporal location, and additional samples are used for adjusting them that do not affect the operation of the correction unit, the position of the samples is set optimally with different linear distortions of the input signal Claim 1. A device for clock synchronization of a discrete information receiver containing serially connected master oscillator, correction unit and frequency divider, serially connected input adder, error signal conditioner and scaling unit, serially connected analog-to-digital converter and input shift register, as well as subtractor, n -channel block multipliers and p signal processing circuits consisting of a serially connected multiplier, adder and shift register, the outputs of which are connected to the second inputs of the adder, and the outputs of the scaling unit are connected to the first inputs of multipliers p signal processing circuits, the outputs of the input shift register are connected to the corresponding second inputs of multipliers p signal processing circuits and inputs of the n-channel multiplier unit, the second inputs of which are connected to the outputs the shift registers of the corresponding p signal processing circuits, and the outputs of the n-channel multiplier block are connected to the inputs of the input adder, the output of the frequency divider is connected to the clock input Odam shift registers n signal processing circuits, the analog-to-digital converter input being a device input, characterized in that, in order to improve synchronization accuracy, the first and second additional shift registers and the first additional multiplier, as well as the second additional the multiplier and accumulating adder, while the inputs of the first additional p of the head of the shift and the second additional multiplier are connected to the outputs of the input adder, the output of the sign p The first additional shift register is connected to the second inputs of the first and second additional multipliers, the outputs of which are connected via a serially connected subtractor and accumulating adder to the control input of the correction unit, the output of the frequency divider is connected to the clock input of the accumulating accumulator, and the additional output of the frequency divider is connected to the clock inputs of the analog-digital converter, the input shift register and the first and second additional registers shift . 2. A device according to claim 1, characterized in that the input shift register contains 2 bits, with the outputs of odd bits being the outputs of the input shift register. but