SU1622834A1 - Digital phase meter - Google Patents

Abstract

The invention can be used to measure the base shift with asymmetric harmonic constraints. The purpose of the invention is to improve the accuracy of phase shift measurement. The digital phase meter contains limiters I and 2, inverter 3, E-triggers 4 and 5, semi

Description

SS

(L

adders 6-9, control unit 10, including triggers P.-14, element 15, inverter 16, master oscillator 17, time master unit 18, single-oscillators 19 and 20, block 21 defining the maximum code, subtractor 22, inverter 23 characters, sampling block 24, memory register 25, blocks 26 and 27 forms

The measurement of quantizing pulses, containing elements 28-31, and measurement blocks 32 and 33, containing counters 34-37 and blocks 38 and 39 of the subtraction. The goal is achieved by eliminating dead zones by eliminating undefined states of control elements. 10 cl.

thirty

35

The invention relates to a technique of radio measurements and is intended for 15 phase shift measurements with asymmetrical limitations of harmonic signals.

The aim of the invention is to improve the accuracy of phase shift measurement. 20

Figure 1 shows a functional diagram of a digital phase meter; 2 shows an exemplary embodiment of the time of the emitting block; in fig. 3 shows an example of the execution of a task block with a maximum code of 25; in fig. 4 shows timing charts explaining the operation of the digital phase meter; in fig. 5 illustrates the characteristics of the primary and secondary measurement channels and the method for correcting the measurement result; in fig. 6 and 7 are timing diagrams for the formation of additional sequences on E-triggers; on Fig - characteristic of a digital phase meter with a dip near 180 :; in fig. 9 and 10 are timing diagrams explaining the operation of the control unit in the presence and absence of an additional sequence on the corresponding E-flip-flop. Digital (a laser meter contains limiter amplifiers 1 and 2, inverter 3, E-triggers 4 and 5, half-summers 6 - 9, control unit 10 containing the first 11, second 12, third 13 and fourth 14 triggers, And 15 element and inverter 16 , setting generator 17, time setting unit 18, one-shot 19 and 20, block 21 dropping the maximum code, 22 subtractions, inverter 23 characters, sampling block 24, register 25 of memory, blocks 26 and 27 of generating quantizing pulses performed on elements 28-28, and measurement blocks 32 and 33, performed respectively on counters 34.35 and 36, 37 and blocks 38 and 39 subtracted neither

The output of the amplifier limiter 1 is connected to the inputs of the installation E-trig40

45

55

0

five

0

5 Q

0

five

five

4 and 5 and the first inputs of the half-adders 6 and 3. The output of the amplifier limiter 2 is connected to the zero input of the E-flip-flop 4, the first input of the half-adder 9 and the input of the inverter 3, the output of which is connected to the zero input of the E-flip-flop 5 and the first input of the half-adder 7 The inverse output of the E-flip-flop 5 is connected to the clock input of the flip-flop. which is the first input of the control unit 10. The direct outputs of the E-flip-flops 4 and 5 are connected respectively to the second inputs of half-adders 6 and

7 and the second inputs of half adders

8 and 9. A forward output of the E-flip-flop 5 is also connected to the clock input of the flip-flop 13, which is the second input of the control unit 10. Trigger Outputs

12 and 13 through the element 15 are connected to the information input of the trigger 14. The outputs of half-adders 6-9 are connected respectively to the first inputs of the elements 28.29 and 30.31 of the blocks 26 and 27 of the formation of quantizing pulses, the second inputs of which are interconnected the generator 17 and the input of the timing unit 18, the output of which is connected to the input of the one-shot 19, the third inputs of the elements 28 to 31, to the zeroing input of the trigger 11, which is the input of the gating of the control unit 10, and through the inverter 16 with the clock input of the trigger 14.

The output of the trigger 11 is connected to the inputs of zeroing triggers 12 and 13.

The outputs of the And 28 and 29 elements of the quantizing pulse shaping unit 26 are connected to the counting inputs of counters 34 and 35 of the measuring block 32, the outputs of which are connected respectively to the inputs of the subtracting unit 38, and the outputs of the And elements 30 and 31 of the quantizing pulse shaping unit 27 inputs of counters 36 and 37 of measurement unit 33, the outputs of which are connected respectively to the inputs of calculation unit 39.

The zeroing inputs of counters 34-37 are connected to the zeroing input of the trigger 14, which is the zeroing input of the control unit 10, the clock input of the trigger 11 and the output of the one-shot 20, the input of which is connected to the output of the one-shot 19 and the clock input of the memory register 25, the information input of which is connected to the output of sampling unit 24, the selection input of which is connected to the output of flip-flop 14, which is the output of control unit 10. The information output of the subtraction unit 33 of the measurement unit 32 is connected to the first input of the subtraction unit 22, the second input of which is connected to the output of the maximum code setting unit 21, and the output to the first input of the sampling unit 24, the second input of which is connected via a sign inverter 23 38 subtracting, and the third and fourth inputs, respectively, with the information and sign outputs of the subtracting unit 39 of the measuring unit 33.

The timing driver unit 13 (Fig. 2s can be performed on a shift counter 40 with a n size and RS trigger 41, the first output of the shifting counter 40 is connected to the installation input, and the k-th output is connected to an input fault of the KZ-trigger 4) .

The maximum code setting unit 21 (FIG. 3) can be executed as a set of keys 42 with chatter suppression.

The triggers 11-14 can be executed as D-triggers, and the logical inputs 1 to 13 are constantly fed to the information inputs of the triggers.

Digital phase meter works as follows.

Harmonic signals (ig.4a, b) are fed to the inputs of limiter amplifiers 1 and 2, from the outputs of which rectangular pulses are removed (in fig.4b, d), the fronts of which coincide with the instant of crossing the harmonic signals of the threshold level of amplifiers limiters and 2.

The pulses from the output of the amplifier-limiter 1 are fed to the inputs of the E-flip-flop installation 4 and 5 and the first inputs of half-adders 6 and 8. The impulse from the output of the amplifier-limiter 2 is fed to the zero input of the E-trigger 4, the first input of the half-adder 9 and the input of the inverter 3, from the output of which the pulses (Fig. 4e) are fed to the input of zeroing the E-flip-flop 5 and the first input of the half-adder 7.

At the same time, at the outputs of the E-flip-flops 4 and i, the first and second additional pulse sequences are formed (fig.4h, 3h). a pulse leading in phase to a sequence of pulses coming from the outputs of amplifiers gels - limiters 1 and 2. At the second l-4th sequence of sequence 4 h) positive, the pulse front is formed by a positive front and negative nt impulse - snipepnyvy -: the pulse front of a phase lagging sequence that is lagging behind the phase, arrives from the outputs of the limiting amplifiers I and 2. With the help of half-adders 6–9, the first additional sequence of the sum modulator two with the pulse sequence g -, i from the output of the amplifier-limiter 1 and the inverse pulse sequence from the amplifier-limiter I, and the second additional pulse sequence is summed modulo two with the pulse sequences from the outputs of the amplifiers of the limiters 1 and .2 s accordingly.

The resulting pulse sequences are received, respectively, at the first inputs of the And 28.29 and 30, 3 elements of the quantizing pulse formation blocks 26 and 27, where they are filled with high frequency pulses of the master oscillator 17 during the gating pulse (Fig. 4 and) specified by the time block 18 (figure 4 k, l, m, n). From the output of the blocks 26 and 27 of forming quantizing impulses, the pulse packets arrive at the counting inputs of counters 34, 35 and 36, 37 of the blocks 32 and 33 of measurement.

The output of the subtraction unit 38 forms a code corresponding to the module and the sign of the phase shift between the pulse sequences at the outputs of the amplifier limiter 1 and the inverter 3, and at the output of the subtraction unit 39 and at the outputs of the limited amplifiers 1 and 2. When Thereby, the characteristic of the azometer at the output of the measuring unit 32 is shifted relative to the characteristic at the output of the measuring unit 33 by 180 ° (Fig. 5a, b).

In order to correct the result obtained from the outputs of measurement unit 32, the code corresponding to the module of the phase difference is subtracted by subtraction unit 22 from the maximum code given by the keys 42 of the maximum code setting unit 21 (FIG. 13), and the code corresponding to is inverted by the sign inverter 23. For the control signal from the 20 output of control unit 10, sampling unit 24 passes the measurement result code from the output of measurement unit 33 or the code of the corrected measurement result from unit 26 to the information input of memory register 25.

The gating pulse duration (Fig. 4i) is formed equal to the required measurement time with the help of 30 RS-flip-flops 4) time by the driver unit 18 as the interval between the appearance of pulses on the first and K-th outputs of the shift counter 40. During the time equal to the interval between the appearance of pulses — on the K-m and n-th outputs of the shifting counter 40; a clock pulse is formed on the one-oscillator 49, with which the measurement result is copied to the memory register 25, 0, and on the one-oscillator 20 — a pulse that flushes the counters 34 - 37 blocks 32 and 33 measurements, block 10 control resetting the phase meter circuit ..45

With phase shifts of harmonic signals (fig. 6a, b) close to 0 and 180, from which a sequence of square impulses is formed (fig. 6b, d), a situation is possible when an additional sequence is not formed on one of the E-triggers 4 and 5 (Fig. 6e, e), then an additional sequence should be formed on the other E-flip-flop.

When forming the output signal of the control unit 10 supplied to the selection input of the sampling unit 24, which passes to the input of the register

25 memory measurement result from the output of the subtraction unit 39 of the measurement unit 33 or the corrected measurement result from the output of the subtraction unit 22 and the inverter 23 characters. Which are formed from the output signals of the limiting amplifiers 1 and 2 (fig.7a, b), the situation may occur when the time interval overlap Ј becomes so small that the corresponding E-flip-flop ceases to generate additional consistency of pulses, at the same time the interval of overlap of these pulses may be sufficient to trigger a block 10 and control because of the different thresholds and time trigger.

Supplying, in order to eliminate the dead zones, to the inputs of half adders 6.7 or 8.9 of the output signal of the E-flip-flop 4 or 5, which did not form an additional sequence, leads to a sharp distortion of the measurement result (i.8a, b) of the corresponding rope. After offsetting the characteristics of the first channel by 130 ° with an inverter 23 characters, the unit 21 sets the maximum code and the unit 22 subtracts the part of the range where the E-flip-flop 5 stops Generating additional error, and the control unit 10 has not yet switched, becomes Bina the characteristic of the phase meter (Fig.Zv).

In the proposed technical solution, the gating pulse (Fig. 9a), generated by the time of the specifying unit 13, zeroes the trigger 11 of the control unit 10, the output signal of which (fig.9) removes the zeroing from the triggers 12 and 13. If the additional sequence at the output of the E-trigger 5 Formed (php) | then a positive pulse front at the direct output of the E-flip-flop 5 (Lig.9v) sets the state to logical 1 flip-flop 12 (fig.9g), and a positive edge of the pulse at the inverse output of the E-flip-flop 5 (fig.9 d) sets state 1 trigger 13 (Figure 9e). If both flip-flops 12 and 13 are set to state 1, then the AND element 15 1 is set at the information input of the trigger b (Fig. 9g). At the end of the impulse, stro bironlni (FIG. 9a) pololitelt

The front of the gated pulse inverted by the inverter 16 (Fig. 9 g) supplied to the clock input of the trigger 14 records 1 therein, which from the output of the trigger 14 (Fig. 9i) is fed to the selection input of the sampling unit 24, which passes to the memory register 25 This is the result from the output of block 39 of subtraction of block 33 of measurement.

If the additional sequence at the output of the E-flip-flop 5 is not formed (Lig. Yua), then during the gating pulse (Fig. 106) at least one of the triggers 12 and 3 is not set to state 1, from the output of the And 15 element to the informational the trigger input 14 is supplied O (FIG. UV). At the end of the gating pulse (Fig. 1Ob), the positive front of the gating pulse inverted by the inverter 16 (Fig. South) fed to the clock input of the trigger 14 records O, which is fed from the output of the trigger 14 to the selection input of the sampling unit 24, which passes to the input of the memory register 25, the corrected result from the output of the subtraction unit 22 and the inverter 23 characters.

The pulse from the output of the one-shot 19 (Fig. 9k, Fig. 10Oe) rewrites the information from the output of the sampling block 24 to the memory register 25. The zeroing pulse from the output of the one-shot 20 (fig.9l, fig.yuzh), which brings the phase meter to the initial state, embeds the trigger 14 (fig.9i) of the control unit 10 and enters the clock input of the trigger 11 by writing to it (FIG. .96), which reset the triggers 12 and 13 of the control unit 10 (fig.9g, e), resetting the control unit 10.

Claims (1)

Comparative tests of digital phase meters showed that the known phase meter, with asymmetry limiting input signals and phase shifts close to 130 °, has a dip in the characteristic of the phase meter 0.05-0.1 wide. The proposed solution makes it possible to eliminate dips in the characteristic of the phase meter at any asymmetry of limiting the input signals at any phase shifts. Invention Formula Digital phase meter containing master oscillator, time master 0 five five 0 the block, the first and second shapers of quantizing pulses, the first, second, third and fourth half-summers; first and second E-flip-flop and, first j and second amplifiers-limiters, memory register, sampling unit, sign inverter, subtraction unit, maximum code setting unit, first and second one-oscillators, first and second measurement units, control unit and inverter, the input of which is connected to the output of the second amplifier-limiter, the first input of the fourth half-adder and the R-input of the first E-flip-flop. and the output is connected to the first input of the second half-adder and the R-input of the second E-flip-flop, the output of which is connected to the second inputs of the third and fourth half-adders, the outputs of which are connected to the first and second signal inputs of the second quantizing pulse generator, and the S-input of the second The E-flip-flop is connected to the first inputs of the first and third half-adders, the output of the first amplifier -o retractor and the S-input of the first E-flip-flop, the output of which is connected to the second inputs of the first and second half-adders cot-dneny with the first and second signal inputs of the first quantizing pulse generator, the clock input of which is connected to the output of the master oscillator, the input time of the master unit and the clock input of the second quantizing pulse generator, the first and second outputs of which are connected respectively to the first and second counting inputs of the second of the measuring unit, the inputs of the first, second and second gammers of quantizing gating pulses are connected to the gating input of the block 5 controls, the outputs of the time of the master unit are connected to the input of the first one-oscillator, the output of which is connected to the clock input of the memory register, the input of the second one-oscillator, the first 0 and the second counting inputs of the first measurement unit are connected to the outputs of the first quantizing pulse generator, the information output of the first measurement unit is connected to the first 5 input block subtract, signed the output through the inverter is connected to the first input of the sampling unit, and the zero input is connected to the zero input of the control unit, the output of the second 0 five 0 one-shot and zeroing input of the second measurement unit, the information output of which is connected to the second input of the sampling unit, the sign output is connected to the third input of the sampling unit, the control input of which is connected to the output of the control unit, the output is connected to the information input of the memory register, and the fourth input is with the output of the subtraction unit, the second input of which is connected to the output of the maximum code setting block, characterized in that, in order to improve the measurement accuracy, the first information input of the control unit is connected to direct output of the second E-flip-flop, the inverse output of which is connected to the second input of the control unit containing the first, S the second, third and fourth triggers, element I and the inverter, whose output is connected to the clock input of the fourth trigger, and the input is the gate input of the control unit and connected to the zero input of the first trigger, whose output is connected to the zero input of the second and third triggers, clock inputs which are respectively the first and second information inputs of the control unit, and the outputs are connected to the first and second inputs of the AND element, the output of which is connected to the information input of the fourth flip-flop, the output of which pry is the output of the block up. and the zero input is connected to the clock input of the first trigger and is the zero input of the control unit. FIG. I 42 to 22 FIG. V o08l Oftflv / J l xfois S oOSLI H / $ E2ngt l h / r / 7 : / -180 /% / l / FIG. 6 7 180 ° Df 180 ° W 9