SU1538239A1

SU1538239A1 - Pulse repetition frequency multiplier

Info

Publication number: SU1538239A1
Application number: SU884367273A
Authority: SU
Inventors: Анатолий Станиславович Тарвид; Виктор Иванович Пономаренко; Владимир Иванович Резник
Original assignee: Предприятие П/Я М-5156
Priority date: 1988-01-21
Filing date: 1988-01-21
Publication date: 1990-01-23

Abstract

Изобретение может быть использовано в устройствах измерительной и вычислительной техники. Цель изобретени - повышение точности и ускорение входа в режим при изменении частоты входного сигнала-достигаетс за счет введени блока 12 синхронизации, выполнени генератора 10 двухтактным, введени счетчиков 4 и 5 импульсов, инвертора 11 и вентил 8 с образованием новых функциональных св зей. Устройство также содержит счетчики 1 - 3,9 импульсов, элемент 6 сравнени кодов, вентиль 7, входную 13 и выходную 14 шины. Приведено описание блока 12 синхронизации. 1 з.п.и. 1 ил.The invention can be used in devices measuring and computing. The purpose of the invention is to increase the accuracy and accelerate the input to the mode when the input signal frequency changes — achieved by introducing synchronization unit 12, making generator 10 push-pull, introducing counters 4 and 5 pulses, inverter 11 and valve 8 to form new functional connections. The device also contains counters 1 - 3.9 pulses, a code comparison element 6, a valve 7, an input 13 and an output 14 bus. A description of block 12 synchronization. 1 zp 1 il.

Description

с первого его выхода блокируетс вен- нератора импульсов опорной частотыfrom its first output, the ventilator of the reference frequency pulses is blocked

и со счетным входом второго счетчика импульсов, второй вход - с входнойand with a counting input of the second pulse counter, the second input - from the input

тиль 17, а сигналом с второго, прошедшим через инвертор 21, - счетчик 15.Til 17, and the signal from the second, passed through the inverter 21, the counter 15.

До прихода следующего импульса на шине 13 импульсы с первого выхода генератора 10 поступают на счетный вход счетчика 3, производ преобразование в код следующего периода входных импульсов, и на счетный вход счечика 2, осуществл преобразование кода, содержащегос в счетчике 1 в период выходных импульсов. Импульсы выходной частоты на шине 14 вырабатываютс по коду целой части, содержащейс в счетчике 1. Поступающий с выхода вентил 7 на счетные входы счетчиков 5 и 1 сигнал обеспечивает изменение упом нутого кода целой части , что приводит к соответствующей коррекции периода выходных импульсов (при условии, что дробна часть не равна нулю).Prior to the arrival of the next pulse on bus 13, the pulses from the first output of generator 10 are fed to the counting input of counter 3, converting the code of the next period of input pulses into the code, and to the counting input of count 2, converting the code contained in counter 1 during the output pulses. Output frequency pulses on bus 14 are generated by the integer part code contained in counter 1. The signal coming from the output of the valve 7 to the counting inputs of counters 5 and 1 provides for a change in the mentioned integer part code, which leads to a corresponding correction of the period of output pulses (provided that the fractional part is not equal to zero).

При увеличении частоты импульсов на шине 13 практически мгновенно увеличиваетс и частота импульсов на шине 14 (с точностью синхронизации блоков 12).As the frequency of the pulses on the bus 13 increases, the frequency of the pulses on the bus 14 also increases almost instantaneously (with synchronization accuracy of blocks 12).

При уменьшении частоты импульсов на шине 13 происходит выработка на шине 14 числа выходных импульсов, равных коэффициенту умножени устройства . Далее происходит блокировка вентил 8 выходным сигналом делител 9, коэффициент делени (коэффициент пересчета) которого, как и счетчика 3, соответствует коэффициенту умножени устройства. При этом происходит линейное нарастание периода выходных импульсов на шине 14 до по влени следующего входного импульса на шине 13, после чего обеспечиваетс выработка точного значени выходной частоты (практически без переходного процесса).When the frequency of the pulses on the bus 13 decreases, the number of output pulses on the bus 14, equal to the device multiplication factor, occurs. Next, the valve 8 is blocked by the output signal of the divider 9, the division factor (conversion factor) of which, like counter 3, corresponds to the multiplication factor of the device. In this case, a linear increase in the period of the output pulses on the bus 14 occurs until the next input pulse appears on the bus 13, after which an exact value of the output frequency is produced (almost without transient process).

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делитель частоты, тактовый вход которого соединен с выходном шиной, отличающийс тем, что, с целью повышени точности при одновременном ускорении входа в режим при изменении входного сигнала, генератор импульсов опорной частоты выполнен двухтактным, в умножитель введены четвертый и п тый счетчики импульсов , инвертор и второй вентиль, выход которого соединен с входом сброса второго счетчика импульсов, второй вход - с тактовым входом делител частоты, вход сброса которого подключен к входной шине, и с выходом инвертора, вход которого соединен с выходом первого вентил и со счетными входами первого и п того счетчиков импульсов, информационные входы которых поразр дно соединены с выходами соответственно четвертого и третьего счетчиков импульсов, входы сброса которых соединены с вторым выходом блока синхронизации, третий вход которого соединен с вторым выходом генератора импульсов опорной частоты, первый вход - с счетным входом третьего счетчика импульсов, третий выход - с входами записи п того и первого счетчиков импульсов, выход переноса первого из которых соединен с входом переноса второго, а третий и четвертый счетчики импульсов соединены последовательно.a frequency divider, the clock input of which is connected to the output bus, characterized in that, in order to increase accuracy while simultaneously accelerating the mode input when the input signal changes, the reference frequency generator is push-pull, the fourth and fifth pulse counters, an inverter and the second valve, the output of which is connected to the reset input of the second pulse counter, the second input - to the clock input of the frequency divider, the reset input of which is connected to the input bus, and to the output of the inverter, whose input one with the output of the first valve and with the counting inputs of the first and fifth pulse counters, the information inputs of which are bitwise connected to the outputs of the fourth and third pulse counters, respectively, whose reset inputs are connected to the second output of the synchronization unit, the third input of which is connected to the second output of the pulse generator reference frequency, the first input - with the counting input of the third pulse counter, the third output - with the recording inputs of the fifth and first pulse counters, the transfer output of the first of which is connected n with the transfer input of the second, and the third and fourth pulse counters are connected in series.

2. Умножитель по п.отличающийс тем, что блок синхронизации содержит счетчик импульсов , счетный вход которого соединен через элемент задержки с первым входом первого вентил и непосредст7153823982. A multiplier of a type distinguished by the fact that the synchronization unit contains a pulse counter, the counting input of which is connected, via a delay element, to the first input of the first valve and 715382398

венно с первым входом блока синхро- блока синхронизации, первый выход низации, второй вход которого соеди- которого соединен через первый ин- не.н с входом сброса счетчика импуль- вертор с выходом первого вентил и сdirectly to the first input of the synchronization synchronization block, the first output of the synchronization, the second input of which is connected via the first inn.n to the reset input of the counter impulse with the output of the first valve and

сов, первый выход которого соединенд тактовым входом триггера, второй вы- с вторым входом первого вентил , с ход - с выходом второго вентил , а информационным входом триггера и с третий выход - с выходом триггера, первым входом второго вентил , вто- при этом второй выход счетчика им- рой вход которого соединен с входом пульсов соединен с его входом разресброса триггера и с третьим входомJQ шени счета через второй инвертор.The first output of which is connected to the clock input of the trigger, the second high with the second input of the first valve, with the stroke with the output of the second valve, and the information input of the trigger and with the third output with the output of the trigger, the first input of the second valve, and the second the output of the counter, whose input is connected to the input of pulses, is connected to its input of the trigger trigger and to the third input JQ of the counting through the second inverter.

Claims

and 3, respectively. Moreover, in the account. Formula of the invention Chiki 5 and 1 are written, respectively, fractional and integer parts of the code of the previous period of the pulses on the bus 13.

The received pulse from the second output of the generator 10 sets the trigger 18 to zero and, passing through the valve 19 to the second output of the block 12, sets the counters 3 and 4 to zero. The second pulse from the first output of the generator 10 changes the states at the first and second outputs of the counter 15 , while the signal from its first output blocks the valve 17, and the signal from the second, passed through the inverter 21, counter 15.

Before the arrival of the next pulse on bus 13, pulses from the first output 20 of the generator 10 are supplied to the counting input of counter 3, converting the code of the next period of input pulses, and to the counting input of counter 2, converting the code contained in counter 1 during the period of output pulses. The pulses of the output frequency on the bus 14 are generated by the code of the integer part contained in the counter 1. The signal coming from the output of the gate 7 to the counting inputs of the counters 5 and 1 provides a change in the mentioned code of the integer part, which leads to a corresponding correction of the output pulse period (provided fractional part is not equal to zero).

With an increase in the pulse frequency 'on bus 13, the pulse frequency on bus 14 also increases almost instantly (with synchronization accuracy of blocks 12).

When decreasing the frequency of the pulses on the bus 13, generation of the number of output pulses equal to the multiplication coefficient of the device occurs on the bus 14. Next is blocking. the insertion of valve 8 by the output signal of divider 9, the division coefficient (conversion factor) of which, like counter 3, corresponds to the multiplication factor of the device. In this case, a linear increase in the period of the output pulses on the bus 14 occurs until the next input pulse appears on the bus 13, after which the exact value of the output frequency is generated (practically without a transient process).

1. A pulse repetition rate multiplier containing the first and second pulse counters, the outputs of which are bitwise connected to the first and second groups of inputs of the code comparison element, the output of which is connected to the first input of the first valve, the second input of which is connected to the first output of the synchronization unit, the first input of which is connected to the first output of ge, 5 non-pulse pulses of the reference frequency and to the counting input of the Second pulse counter, the second input to the input bus, the third pulse counter and frequency divider, t the input actuation of which is connected to the output bus, characterized in that, in order to increase accuracy during simultaneous acceleration of entry into the mode when the input signal changes, the reference pulse generator 25 is push-pull, the fourth and fifth pulse counters, an inverter and a second valve are introduced into the multiplier, the output of which is connected to the reset input 30 of the second pulse counter, the second input to the clock input of the frequency divider, the reset input of which is connected to the input bus, and with the output of the inverter, the input of which is connected to the output of Vågå valve and comprising counting inputs of the first and fifth pulse counters, data inputs of which are connected bitwise with the fourth and third output pulse counters respectively reset inputs 40 which are connected to the second output of the synchronization block, a third input coupled to the second output of the reference pulse generator

45 frequencies, the first input is with the counting input of the third pulse counter, the third output is with the recording inputs of the fifth and first pulse counters, the transfer output of the first of which is connected 5θ to the transfer input of the second, and. the third and fourth pulse counters are connected in series.

2. The multiplier according to claim 1, about l and 55, wherein the synchronization unit contains a pulse counter, the counting input of which is connected through the delay element to the first input of the first valve and directly 1538239 directly to the first input of the synchronization unit * whose second input is connected to a pulse counter reset input, the first output of which is connected to the second input of the first valve, with the information input of the trigger and with the first input of the second valve, the second input of which is connected to the trigger reset input and with the third input of the synchronization block, the first output d is connected through a first inverter with the output of the first valve and a 5 clock input of the flip-flop, the second output - with output of the second valve and the third output - with output flip-flop, the second pulse counter output is connected to its input razre10 sheniya account through a second inverter.