SU1192120A1 - Pulse sequence generator - Google Patents

Abstract

1. PULSE SEQUENCE GENERATOR, containing a reference generator, a digital unit of the clock period and a generator of code combinations, the output of which is connected to the output bus, o tl and h and h. y and with the fact that, in order to expand the functionality and expand the frequency range, a reversible counter, the OR element, the first AND element, the first counter, the D-trigger, the first RS trigger, the second counter, the comparison unit, the second AND element, second RS flip-flop, delay element, tri-element AND element, the summing input of the reversible counter connected to the output of the OR element, the subtracting input connected to the output of the first element AND, and the output to the input of the code combination generator, the counting input of the first counter , tact at the D-trigger input, R-input of the first RS-flip-flop and input of the initial setting of the second counter, the first inputs of the comparison unit are connected to the outputs of the digital clock period, the second inputs of the comparison unit are connected to the outputs of the second counter, and the output is connected to R - the input of the first RS flip-flop, the output of which is connected, to the first input of the second element I, the S input of the second RS-flip-flop is connected to the output of the first counter, and the R input is connected to the inputs of the initial installation of the reversing counter, the first counter and with the input busThe initial installation, and the output of the second RS flip-flop is connected to the R-input of the D-flip-flop and second (the second input of the second element is And, the third input is connected to the output of the reference generator and the first input of the OR element, and the output of the second element And is connected to the input the delay element and the counting input of the second counter, the first; the third input AND of the third element connected to the output of the delay element and the first input of the first element AND, and the output of the third element AND connected to the second input of the OR element, the single output D- trigger connected to w ring input and the first element, and zero output in latch chen connected to the D-input of D-flip-flop, to the clock input of the clock period of the digital set point and a second input of the third AND element ..

Description

2. The generator in accordance with clauses 1, 1 and 2), so that the code generator generator comprises a series generator, whose input is the input of the code combination generator, the information sensor and the coding unit, the first whose input is connected to the nerve output of the serial imager, the second input to the second serial imager and to the information sensor input, the third input is connected to the information sensor output, and the output is the output of the code combination generator.

The invention relates to a pulse technique and can be used, for example, on the reproduction channel of a digital magnetic recording device.

The purpose of the invention is the expansion of functional capabilities due to the acquisition of a sequence of HMnyjibs with its built-in static parameters of phase jitter, as well as the expansion of the frequency range.

FIG. 1 n;) the functionality of the pulse sequence generator circuit was introduced; Fig. 2 shows an example of the acquisition of a code generator;

The generator comprises FIG. ) reference IejiepaTop, digital unit of the clock period 2, generator of code combination 3, reversible counter 4, RSHI element 5, first element 6, first counter 7, D-flip-flop 8, first RS-flip-flop 9, second counter 10, comparison unit 11, the second element And 12, the second RZ-flip-flop 13, the delay element 14, the third element And 15, the output bus 16 and the initial bus bus: Tanon 17, and the summing input of the reversing counter 4 is connected to the output of the element OR 5, I read - to the output of the first element And 6. and the output to the input of the generator of code combinations 3, connected with the input of the first counter 7 clock input G; -trigger 8, B-input of the first RS-tritter 9 and input of the initial installation of the second counter 10, the comparison unit i 1, the first inputs of which are connected to the outputs of the digital clock sensor 2, the second inputs - to the second account

10, and the output - to the R-input of the first -, G-trigger 9, the output of which is connected to the first input of the second element And 12.3-input of the second 1: T; -the trigger 13 is connected to the output of the first counter 7, K-input connected to the inputs of the initial installation of the reversible counter 4 and the first counter 7 and connected to the input bus of the initial installation 17, and the output is connected to the R input of the D-trigger 8 connected to the second input of the second element I 2, the third input of which is connected to the output the reference generator 1 and to the first input of the element OR 5, and the output to the input of the delayed epec and 14, connected to the counting input of the second counter iO, the first input of the third element And 15 is connected to the output of the delay element 14 and to the first input of the first element MOirra And 6, and the output to the second input of the element OR 5, and the single output of the C-flip-flop 8 is connected to the second input of the first element And 6, and the zero output - with the D-input of the same trigger, connected to the clock input of the digital clock, the clock period 2 and the second input of the third element 15, the code combination generator 3 contains a shaper 18, information sensor 9 and coding block 2 0 for the selected recording method, with the outputs of the imaging unit of series 18 being connected to a coding unit 20 and an information sensor 9,

The device works as follows.

In the initial state, the reversible counter 4, the first counter 7 and the second RS flip-flop 13 are in zero states due to the presence of a signal 31 on the initial setup bus 17. The sequence of pulses on the output bus of the device 16 is absent in this case . After removing the signal on the bus of the initial installation 17, the reversible counter 4 starts counting the pulses arriving at its summing input from the reference generator I through the element OR 5. After each recalculation of 2. pulses, where P is any integer depending on the volume of the main generator. reversible counter 4, transfer pulses appear at its output, forming a pulse sequence which is converted in code pattern generator 3 into a code sequence corresponding to the received recording method. Simultaneously, the pulse sequence from the output of the reversible counter 4 is fed to the counting input of the first counter 7 and to the clock input of the B-trigger 8, included in the counting mode. However, trigger 8 does not yet count, but is kept in the zero state, due to the low level at its R input. After recalculating 2 pulses, where E is an integer, a transfer pulse appears at the output of the first counter 7, which sets the second RS flip-flop 13 to one state. At that, the D flip-flop 8 is enabled in the counting mode and the second AND element opens. 12. After that, the device starts operating in the mode of imitation of the phase jitter of the generated pulses. The pulses from the reference generator 1, having passed through the second element 12, are fed to the counting input of the second counter 10, the output state of which is compared on the comparison block 11 with the output state of the digital master of the clock period 2. The binary number at the outputs of the digital master of the clock period 2 is determined The value of the phase shift of the next pulse generated at the output of the reversible counter 4 is given. Dp of obtaining the noise distribution of the phase jitter, the digital unit of the clock period 2 is made in the form of a pseudo generator Aina maximum length sequence. In this case, the number of its bits m is chosen such that 2 i 2, where h is the number of bits of the reversible counter 4. 0. 4 The second counter 10 counts the output pulses of the reference generator. When counting K pulses, where K is the number recorded in the digital sensor of the clock period 2, a comparison signal is generated on the code of the comparison unit I1. At the same time, in order to fulfill the comparison conditions, the number of bits of the second counter 10 must be greater than or equal to the number of bits of the digital setter of the clock period 2. From the moment the second trigger 13 is set to one state to the time the comparison signal is generated at the output of the comparison unit 1I through delay element 14 and the second element AND 15 will also pass K pulses that are added on the OR 5 element to the main pulses of the reference generator 1. The comparison signal from the output of the comparison block 11 sets the first trigger 9 to the zero state and the second element AND 12 is closed. The transfer pulse at the output of the reversible counter 4, formed in this case by K pulses before the previous one, switches the G-trigger 8 by its clock input to the one state, sets the second counter 10 to the zero state and the first trigger 9 to the one state In this case, the digital master of the clock period 2 whose clock input is connected to the zero output of the D-flip-flop 8, retains its previous state and changes it only the next time the G-flip-flop 8 is switched from one state to zero. This mode of operation of the digital unit of the clock period 2 is obtained when building it on the registers operating on the leading edge of the clock signals. Further, the process of forming the phase shift of the output pulse described above is repeated, except that the pulses from the delay element 14 go through the first element 6 to the subtracting input of the reversible counter 4, the next transfer pulse at the output of this counter is formed on the K pulses later than the previous one and sets the second counter 10 to the zero state, first trigger 9 to the single state, and also switches the D-trigger 8 from the single state to the zero state. At the same time, the digital master of the clock period 2 changes its state and, at its outputs, according to pseudo-random law, generates a new number to specify the next value of the phase shift.

The code combination generator (Fig. 2) works as follows. The input pulse sequence is divided into two series in the JQ series driver, 18 with a counting trigger operating on the rear

front of clock signals, and two elements And, the sensor of information 19, which can be the same pseudo-random sequence of maximum length, works in one of the series and generates potential information at its output that goes to the coding unit 20 ( coding block 20 can be constructed in accordance with the accepted recording method).

Claims (1)

1. A PULSE SEQUENCE GENERATOR, comprising a reference oscillator, a digital clock controller, and a code combination generator, the output of which is connected to the output bus, about the power of -. In order to expand the functionality and expand the frequency range, a reverse counter, an OR element, a first AND element, a first counter, a D-trigger, a first RS trigger, a second counter, a comparison unit, a second element are introduced into it And, the second RS-trigger, the delay element, the third AND element, and the summing input of the reverse counter is connected to the output of the OR element, the subtracting input is connected to the output of the first AND element, and the output is connected to the input of the code combination generator, the counting input of the first counter, the clock input D- trigger, R — input of the first RS — trigger and input of the initial installation of the second counter, the first inputs of the comparison unit are connected to the outputs of the digital clock controller, the second inputs of the comparison unit are connected to the outputs of the second counter, and the output is connected to the R-input of the first RS-trigger whose output is connected to the first input of the second AND element, S — the input of the second RS-trigger is connected to the output of the first counter, and R — the input is connected to the inputs of the initial installation of the reverse counter, the first counter and the input bus of the initial installation, and you the stroke of the second RS-trigger is connected to the R-input of the D-trigger and the second input of the second AND element, the third input of which is connected to the output of the reference generator and to the first input of the OR element, and the output of the second element подключен is connected to the input of the delay element and to the counting input of the second counter, with the first input of the third AND element connected to the output of the delay element and to the first input of the first AND element, and the output of the third AND element connected to the second input of the OR element, the unit output of the D-trigger connected to the second input of the first AND element, and zero the D-trigger's output is connected to the D-input of the D-trigger, to the clock input of the digital clock controller and to the second input of the third