SU1580339A1 - Device for information input - Google Patents

Abstract

The invention relates to computing and can be used to control the quality of communication channels when testing channels and their terminals. The purpose of the invention is to increase the reliability of the device and the expansion of its functionality due to the input of signals with different types of code symbols, variable forms of words and pauses. A block of switching elements 1 is introduced into the device, by means of which the signals that form the technical specifications for the operation of the device and the information entered are defined in a static way. The buffer register 8 stores the job during the operation cycle, distributes it to the blocks forming pauses 10 to form the rewriting signal 11, and controls the demultiplexer 24 words. The task contains information about the type of code symbols, the format of words and pauses, the number of words in arrays. The input information is stored in the RAM 15 and when the generator 17 is turned on, it is overwritten into the shift register 23, where it is converted into a sequential form. Further, through the multiplexer 24 words and one of the drivers of the code symbols 12 and 13, it is inserted into the channel. 1 hp ff, 11 ill.

Description

the second group - with the register 8, the impulse of the output at its output by a message according to the lines n possible formats the address in the counter of 14 addresses,

pauses in this work cycle, and also the address change occurs as shown

element And 29, the first input is connected — in FIG. 9 through 157 not from the arrival of a negative impulse, This is the delay time 20 of the response of the NAND element and the counter 14 performed at K155 sec35

with the decoder 20, the second - with the register 8.

The shaper 13 of code symbols (Fig. 3) contains elements I 30 and 31, three analog switches 32-34, elements NOT 35 and 36, element A 37. Switches switch the positive and negative power sources to a common point of time, defined the control inputs of the switches are And 37 and 31 elements. During the pauses between positive and negative pulses through an analog switch 34, controlled by an inverter 35, this common point (output 25 of the unit and the device as a whole) switches to a common power point,

The shaper 12 code symbols (Fig, 4) contains the element LLI-HE 38, four elements AND 39-42, the element ALL-HE 43, the element OR 44, D-flip-flop 45. The block forms a two-level phase-shifting Q-pooled code with a sync signal with a duration of 3T 37/2 cycles of different polarity. The output of block 26 is the second output of the device as a whole.

The shaper 1 6 impulse recording (Fig. 5) contains the inverters 46-4U, the elements 50 and the inverter 51. The shaper generates a narrow pulse through the cut of the signal from unit 1.

The demultiplexer 24 words (Fig, 6) contains the element NOT 52 and the elements L 53 and 54.

The device works as follows

In Oloka 1 of switching elements, a technical task is set for the device's operation, the ocher / first information1

O (Efficiency (I-Y.J.-JM FULL g NODIMSH O COD. H, about h with mgsine, format

rii

The write pulse shaper (Fig. 5) generates a short pulse.

25 through the cut of the input signal. Executed on logic elements ;; That K155 series, it forms a short pulse with a width of 59 not every 37 from the cutoff of the input signal. This short 30 pulse is used to record information in memory 15 performed on the K155RU2 microcircuits. Since the entry is made at the previous address, the first address is the zero address 0000, Therefore, when you enter two words, the last address is 9001, The number of address lines from the 14-address counter to the memory address inputs. 15 equals L.

..- С1о.,

where E is tsol part, -ms ia,

In fig „10 bye tu. ii.sin records: Record 1 and Record.

At the output of the counter 14 ip

45 records is a unit, with the second recording it is zeroed; on.,: ON from the output of the decoder 22. When the number of layers to the decoder is expressed, the zero signal of the counter 14 and the signal

50 enable the preset of the subtracting counter 21, And when the number of layers K-1 appears, the unit at the input of the driver 10, This signal is hereinafter referred to as XI.

A clock counter 19 counts clock cycles and zeroes. YI from the output of formirol ch. (.Ii, 4 1). From the AU signal, it is used to determine the value of the signal through the AND-HE element 9 for more accurate 3 55

35

Q

rii

The write pulse shaper (Fig. 5) generates a short pulse.

25 through the cut of the input signal. Executed on logic elements ;; That K155 series, it forms a short pulse with a width of 59 not every 37 from the cutoff of the input signal. This short 30 pulse is used to record information in memory 15 performed on the K155RU2 microcircuits. Since the entry is made at the previous address, the first address is the zero address 0000, Therefore, when you enter two words, the last address is 9001, The number of address lines from the 14-address counter to the memory address inputs. 15 equals L.

..- С1о.,

where E is tsol part, -ms ia,

In fig „10 bye tu. ii.sin records: Record 1 and Record.

At the output of the counter 14 ip

5 records there is a unit, at the second record it is zeroed; on.,: ON from the output of the decoder 22. When the number of layers to the decoder is expressed, the zero signal of the counter 14 and the signal

0 enable the preset of the subtracting counter 21, And when the number of layers K-1 appears, the unit at the input of the driver 10, This signal is hereinafter referred to as XI.

A clock counter 19 counts clock cycles and zeroes. YI from the output of formirol (.ii, 4 1). From the AU signal is used to determine the value of the signal through the AND-HE element 9 for better control 3 5

715

counter 14 addresses in read mode from memory,

To form a signal Y1 in block 10, the signals indicated in FIGS. 10, XI, X2, X3, X4, X5 are used: XI is the end of the array that is formed at the output of the decoder 22, which interprets the K-1 state of word counter 21 ; X2 - the end of the pause between the three-level MESSIES; ХЗ - the end of the pause between words; X4 - the end of the word of the phase-shift code (20 bits); X5 - the end of the pause between the masses

eight

Y2 X1X2X6 with a three-level code; (3)

Y2 XIX5X6 with phase-shift keying. (four)

A Y2 signal is generated on the elements.

zi

The narrow pulses in FIGS. 10 and I are shown in conventional widths, in fact their width is much smaller. The leading edge of the narrow pulses X2, X3, X4, X5 appears when a certain number forms at the output of the decoder 20, and the back front immediately after

You have a phaeomanipulated code, 5, counter zeroing. In this way

The signals X2, X5 are formed; the forma-width of narrow pulses is equal to the sum

11 pauses (Fig. 2). In the buffer delay time of operation, the register 8 stores information about the for-elements of the imaging unit 10, and the number of pauses. For example, consider the input of the counter 19, and descramble when, i.e. formats pauses drto 20,

equal 4Т, 8Т, 16Т between three-level code words and respectively 8Т, 16Tj 32T between arrays, where T is the pulse period from the trigger output. Using the circuit shown in FIG. 4, the code symbols of the two-level neural phase of the manipulation code and the sync signal of 3 are formed

Using the scheme shown in FIG. 4, the code symbols of the two-level phase of the manipulation code and the sync signal of duration 3 are formed.

18, At the outputs of the decoder 20 in each case — 25 clocks with 3/2 clocks of different polarity (FIG. 8). This is done as follows. During the first clock cycle from the trigger 18, which is fixed by the decoder 20, the initial signal from the output of the demultiplexer 24 (e.g., logical 1) is output, during the second, fourth and all subsequent to the twentieth clock cycles, the output signal is fed to the device 43 where 1 is shown as negative, during the third clock cycle, the output signal 40 from the output of the demultiplexer (for example, logical O) is fed to the output again. Consequently, to form a word with a sync signal, the original info In order to form a bipolar three-hold in the first three bits or a level code, the signal Y1 is formed by 45 combinations of 110, or 001. In the former 10 by the formula, since the information with you1 X1X2X3 + X1X2 (1)

On the elements NOT, ZI, 2I, 2ILI,

Prk forming phase manipulation of single pulses at the moment of counting the numbers 20, 24, 36, 40, 48, 64 (Fig. 7). The number 20 is used as the X4 signal in block 10, the number 24, as X5 with a pause between the arrays of the phase-ed manipulated code 4T, the number 36 as the X. with a 4T pause, the number 36 as the X. with a 4T pause. when the pause is 8T or as X2 when the pause is 4T between words, the number 48 is like X3 when the pause is 16T or like X2 when the pause is 8T between words, the number 64 is like X2 when paused by the words 16T.

The number of inputs of the decoder 20 (t, e, the number of outputs used counter

19) is determined by the formula t E1ovg (3242T (s, i) + 1

By

logical

With a strong front, the logical O move of the demultiplexer 24 lags slightly behind the pulses from the output of the trigger 8 at the outputs of the elements OR-NOT 43, AND 41 and 44, the appearance of spurious narrow pulses is possible. To eliminate false alarms, the circuit is supplemented with a D-trigger 45, the control input of which receives a phase-shift keying is the code from the output of the OR 44 element, and the synchronizing input is received by double-frequency clock pulses from the output of the IT generator,

code, the signal is formed in the imaging unit 10 by the formula

Y1 X1X5 + X4X1X5% (2)

In the driver 10, a generator stop signal is also generated during a one-time operation. This mode is set by the presence of the Hb signal from the buffer register 8.

 - single mode;

 - cyclic

Using the scheme shown in FIG. 4, the code symbols of the two-level phase of the manipulation code and the sync signal of duration 3 are formed.

 3/2 cycles of different polarity (Fig. 8). This is accomplished in the following manner. During the first one, from trigger 18, which is fixed by encoder 20, the output from demultiplex 24 (for example, logical 1) is output, the second, fourth and all subsequent to twentieth clock cycles are output from output 43 phase shift signal, gd 1, is denied

logical

telny front, logical o

The motion of the demultiplexer 24 lags slightly behind the pulses from the output of the trigger 8 at the outputs of the elements OR-NOT 43, AND 41 and 44, the appearance of spurious narrow pulses is possible. To eliminate false positives, the circuit is supplemented with a D-trigger 45, the control input of which receives the phase-shift key code from the output of the OR 44 element, and the clock input — a double-frequency clock from the output of the IT generator,

In the imaging unit 13, the code symbols of the three-level code are formed.

(Fig. 10), Analog Switches 32 and 33 switch a positive and negative source to output 25, and during times of pauses between negative and positive pulses and pauses between words and arrays, switch 34 switches output 25 to a common power point.

Information on the type of code symbols is also delivered to the 17 clock pulse generator, which pulses at 2 MHz or 96 kHz, respectively. When the generator starts, the serial information from the shift register 23 is transmitted through the demultiplexer 24 words to one of the corresponding PCS1 or PCS2 drivers (Fig , 6

Claims (1)

1. A device for entering information containing a buffer register, a subtracting word counter, a group of inputs of the preset which is connected to the first group of outputs of the buffer register, an address counter, the first decoder, the input of which is connected to the output of the subtracting word counter, RAM, shift register, information the input of which is connected to the output of the RAM, a clock pulse generator, a clock pulse counter, a shaper, a trigger, a write pulse shaper, characterized in that, in order to increase neither the reliability and expansion of the device’s functional capabilities due to the input of signals with different types of code symbols, varying formats of words and pauses, a rewrite signal shaping unit, a second decoder, a switching element block, an AND-NOT element, a word demultiplexer, the first and second blocks forming code symbols, the first and second outputs of the switching elements block are connected to the first and second information inputs of the buffer register, and the first output is also connected to the first control By the entrance clock generatorj the first and second groups of outputs of the switching elements block are connected to the first and second groups of information inputs of the buffer register, the third output of the switching elements block is connected to the input of the imaging unit 10 five 0 the recording pulse and the first input of the NAND element, and the third group of outputs of the switching elements block is connected to the information inputs of the main memory, the first and second information outputs of the buffer register are connected to the first and second information inputs of the rewriting signal generation unit, the first output of which is connected to the zeroed the input of the counter of clock pulses and the second input of the NAND element. and the second output With the second control input of the clock pulse generator, the second group of information outputs of the buffer register with the group of information inputs of the pause generator, the output of the NAND element is connected to the clock input of the subtractive counter layers and the clock input of the address counter, the input group of which is connected to a group of addressable inputs of the RAM, whose recording input is connected to the output The 5th house of the write pulse former, the third, fourth and fifth informational 1 moves of the overwriting signal generator are connected respectively to the first, second and third informational outputs of the silencer, the sixth to the first output of the first decoder, the second output of which is connected to the output address counter and the enable input of the preset of the subtracting word counter of the clock pulse generator is connected to the first clock input of the first shaper of code symbols and to the trigger input, the output of which it is connected to the second clock input of the first shaper of code symbols, to the clock input of the second shaper of code characters, to the clock input of the shift register and to the clock input  The clock counter house, the outputs of which are connected to the inputs of the second decoder, whose corresponding outputs are connected to the control input of the shift register, is connected to the control inputs of the first code symbol generation unit, to the control input of the second Code Character Former, with a group of information inputs the pause generator and the seventh input of the rewrite signal generation unit; the information input of the words de-multiplexer is connected to the information | shift register output, control input - with the second output, bu0 five 0 55 The first and second information outputs of the word demultiplexer are connected to the information inputs of the first and second code symbol generation blocks, the outputs of which are the outputs of the device, 2, the apparatus according to claim 1, wherein the first block of forming the code symbols comprises. the four AND elements, the two OR elements, the OR element, the D trigger, the first inversion input of the first AND element, is connected to the first input of the second AND element, and is the first clock input of the block, the second input of the first AND element is connected to the second inverse the input of the second element I, with the first input of the block . go From 6 / Yuku) From the block I the house of the third element AND is the information input of the block, the outputs of the first and second elements AND are connected to the inputs of the OR-NOT element, the output of which is connected to the first input of the fourth element AND, the second input of which is connected to the inverted input of the third element AND way out the second element OR NOT, whose inputs are the control inputs of the block, the output of the third and fourth elements AND are connected to the inputs of the OR element whose output is connected to a D-flip-flop input, the clock input of which is the second clock input of the block, and the output is the output of the block. 38V From bona 17 From block 1 Al l l a so U CH7 CHV LZ (t) from block 19 Kbaoku15 five/ FIG. eight Rie in Record2 1 -S. 3 for g J Ј A- / JT ЈлЈОХ4 otrlf. SA. fff xs fa ss. & xf . v / x Vl.O. SlrfX 6. f to 6Sh Ze Hod FIG. YU 0 1 / JJJJJf (