SU1392625A1 - Device for transmitting information by pseudo-random signals - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the speed and reliability of work by excluding idle cycles from the generated sequence and faulty situations. The device contains RS-flip-flop (t) 1, shift register (P) 3, adder 6 modulo two, inverter 7, generator 8 clock pulses, binary counter (DC) 9, code comparison block 10, cipher input block 17, encoder 18, electr OR-NOT 19, block 20 of inverters, block 21 T. Keys 2 and 3 are entered, block 4 of the ban, RS-T 11 and 16, block 12 of the series of the 1st and last pulses of the series, el - OR 13, two Short Pulse Shaper (FCI) 14 fronts, two FCI 15 slice. The increase in speed is due to the fact that all digital devices, in particular DS 9, are nullified by the last pulse (front) of the generated clock pulse sequence, not waiting for DS 9 to overflow, and because additional time is excluded recording the message signal in block 17, since this time is allocated between the cutoff of the 1st and the front of the last pulse of the clock series. Failure situations are eliminated due to the prohibition of the supply of a clock pulse to P 5 during the recording of a message signal into it and by excluding the recording in block 17 at the instants of time when I get I111I Scheduling and Reset signals. When 1 input is stopped, the RS-T 11 switches to the state O, the key 2 closes, stopping the passage of clock pulses from the generator 8. 3 Il. Aofxoff (L co) y O5 ke el Fm. /

Description

The invention relates to radio engineering and can be used in the transmission of information flows characterized by a certain static redundancy.

The purpose of the invention is to increase the speed and reliability of operation by excluding non-working cycles from the generated sequence and faulty situations.

Fig. 1 is a block diagram of a device for transmitting information by a pseudo-random signal; Fig 2 is a structural electrical block cipher block circuit; FIG. 3 shows a structural electrical circuit of the inverter.

The device contains the first RS of signal 1 at the input. The device is started by applying a signal 1 to the S input of the second RS flip-flop II, the output of which generates a voltage that opens the first key 2, the output of which receives the clock pulses generated by generator 8 which arrive at the input of the first key 2, from whose output, if the device is included in the start mode, are fed to the input of the second key 3 and through it to the input of the binary counter 9.

The latter counts the number of clock pulses and transmits the information in the parallel code to block 10. If the binary codes that are applied to the inputs of block 10 match and match, they coincide.

trigger 1, first 2 and second 3 keys, 20 em signal I to the first RS flip-flop 1,

BANE element 4, shift register 5, cyi-fMBTOp 6 modulo two, inverter 7, clock generator 8, binary counter 9, code comparison unit 10, second RS flip-flop 11, block 12 for extracting the first and last pulses of a series, OR element 13, the first 14-1 and the second 14-2 shapers of short 1-1 pulses of the front, the first 15-1 and the second 15-2 shapers of short cut pulses, the third NJ-flip-flop 16, block 17 of the input digit, the encoder 18, the element OR NOT 19, block of 20 inverters, inverters

20-1, 20-2, ..., 20-k, block 21 trigger-35 owls from generator 8, passing through the ditch, triggers 21-1, 21-2, ..., 21-k. public first key 2. From the output, the second, the cipher input block 17 contains in each channel an RS flip-flop 22, a nepBbrti element OR 23, the first element

key 3 key formed sequence (series) of clock pulses fed to the inputs elements

And 24, the second element OR 25, the second 40 BANKS 4 and block 12 for the allocation

element and 26, the third element and 27,

fourth element and 28 repeater

29 voltages Inverter 7 contains

element BAN 30, element OR 31,

the key 32, the inverter 33.

A device for transmitting information by pseudo-random signals operates as follows.

Depending on the desired length of the first and last impulses in s rii. The selected first pulse with a gray front edge through the first short pulse generator of the front 45 14-1 starts the readout block 17 and at the same time, the time required to read the information and enter it in the parallel code of the black encoder 18 to the register 5, translates

first and last pulses in a series. The selected first pulse of the leading edge through the first driver of short pulses of the front 45 14-1 launches the readout unit 17 and simultaneously for the time required to read the information and enter it in parallel code through the encoder 18 into the register 5, translates

cutting the pseudo-random sequence of the QAAPRET 4 element into the locked state (SRP) in block 21 of the flip-flops, thereby preventing the passage

setting the length of the cut-off of the memory bandwidth of the write-clock pulse to the clock Ssdviet in binary code, the number of elementary inputs of the register 5 and the exclusion signals (bits). Information with the possibility of a bad situation. Posiz Plokp 21 arrives parallel to the 55th end of the recording of the information of the fn Plock 20 law, where it inverts the pret and is removed and the register 5 transforms into

c, and then it is fed to the inputs of the 1P block. Prered start of operation the digital elements of the device are zeroed by 5

0

which goes from state O to state 1. As long as the first RS flip-flop 1 is in state o, i.e. before the arrival of signal 1 at its input, from the inverse output of the first RS flip-flop 1, signal 1 is fed to the control input of the second key 3, allowing the passage of clock pulses through it. When the first RS-flip-flop 1 arrives at the S-input 1 from the output of block 10, it outputs a signal O on the inverse output that prohibits 3 clock pulses from the generator 8 passing through the open first switch 2 from passing through the second key.

key 3 is a generated sequence (series) of clock pulses from generator 8 that have passed the first open public key 2. From the output

owls enters the inputs

first and last pulses in a series. The selected first pulse of the leading edge through the first shaper of the short pulse of the front 14-1 starts the reading unit 17 and simultaneously for the time required to read the information and enter it in parallel code through the encoder 18 into the register 5, translates

the JAAPRET element 4 in locked state is the mode of shifting the recorded content. Allocated at the second input of unit 12 last t.tulse through the element

3

or 13, to the second input I (before starting operation), a signal 1 is sent from the input Setting the device zero, arrives at the R input of the binary counter 9 and wraps it, at the R input of the first RS flip-flop 1 and switches it to the O position, being prepared for the next working cycle, and at the R-input of the register 5, its work on the formation, together with the adder 6, included in the feedback circuit, of a pseudo-random sequence was stopped. The S and R inputs of the third RS flip-flop 16 receive short positive pulses, respectively, from the first shaper 15-1 short cut pulses and the second shaper 14-2 short front pulses, therefore, a positive pulse is generated on the third RR flip-flop 16 the duration of which is equal to the time between the first cut and the front of the last pulse of the sequence. By this impulse, the block 17 is transferred (via the synchronization input) to the mode of receiving information of the next message, i.e. no additional time is required to receive information. In block 17, voltage followers 29 provide isolation between the circuit that sends a Reset signal to the R-inputs of the flip-flops 22 and information inputs to the R-inputs of these flip-flops.

Because of the need to send a message in block 17, one of the triggers 22 is given a signal. If the signal is given at a time when the block 17 is open, the corresponding trigger 22 receives and stores the received information on the synchronization input. Each trigger 22 provides the setting of two messages: respectively, when the signal is applied to the S input (set to 1) and to the R input (set to O). If the signal arrives at the S-input, then block 17, by the signal Read coupling, signals 1 to one of the inputs of the encoder 18, the output of which goes to register 5 in the parallel code and receives the first bits of the memory bandwidth.

Thus, the encoder 18 sets the initial conditions for the operation of the register 5. At the same time, the block 17 outputs a signal 1 to one of the inputs of the element OR NOT 19, which gives the signal

inverter 7 and vk.gochta

five

i:

0

If the signal arrives at the R-input, then block 17, on a signal Schity, informs one of the encoder's inputs.

18 signal 1, and one of the inputs of the element I.Sh1-IE 14 is a signal P. From the output of the element ILT-1-NK 1Ч to the yugtion control, the input of the inverter 7 receives a signal, the switching-on inverter 7, Register 5 registers the the sequences at the moments of time determined by the arrival at its first input of clock pulses from the output of the second key 3 through the open element BAN 4. In the adder 6, the modulo two corresponding bits, for example, the third and fifth bits of the register 5, are added. adder 6 information is recorded in the first th discharge register 5. The output register 5 receives elementary signals to an information input of the inverter 7.

If the control input of the inverter 7 is fed from the output of the element OR NOT

19 signal 1, the sequence is formed without inversion. If the signal O is given at its input, then the SRP elementary signals are inverted. From the output of the inverter 7, the direct or inverse sequence, respectively, enters the link or the input of the radio transmitting device.

Inverter 7 operates as follows.

If the information input is supplied by the formed SRP and the control input is signal 1, the BAN 30 element is locked and inverted by the inverter 33 of the SRP to the first input of the OR element 31 and is not output to the inverter 7. The key 32 is open and non-invertible PSP through the element OR 31 is fed to the output of the inverter 7.

If the control signal O is given, the key 32 is locked and the non-inverted memory bandwidth is not output, and the prohibition element 30 is open and inverted by the inverter 33 memory bandwidth OR 31 passes to the output of the inverter 7.

Moreover, the increase in speed is due to the fact that all the digital elements of the device, in particular, the binary counter 9, have rolled 5

five

0

five

the last pulse (front) of the generated sequence of clock impulses, without waiting for the binary counter 9 to overflow, and also because the additional time for recording the message signal in block 17 is eliminated, since this time is allocated between the first cut and the front of the last pulse; product series, i.e. practically during the entire time of formation of the memory bandwidth and placing it into the communication line. Failure situations are eliminated due to the prohibition of the clock pulse input to the register 5 during the recording of the message signal into it and by excluding the recording of the message signal in block 17 at the times when the read and reset signals are applied to it.

When signal 1 is applied to the device Stop input, the second RS flip-flop 11 goes to the state O, the first key 2 is closed, stopping the passage of clock pulses from the generator 8 output.

Formula inventions

thirty

35

1. A device for transmitting information by pseudo-random signals, comprising a clock pulse generator, a serially connected binary counter, a code comparison unit and the first RS flip-flop, an inverter unit and a trigger unit, the codes of which are connected to the corresponding inputs of the inverters unit, the codes of which are connected to the corresponding .Q by the second inputs of the comparison unit, serially connected cipher input unit, encoder, shift register and modulo two, the second input and output of which are connected accordingly but to the second output and the information input of the shift register, the element OR NOT, whose inputs are connected to the second outputs of the cipher block, the inverter, the control input of which is connected to the output of the element OR NOT, is the output of the device, characterized in that in order to improve performance and reliability by

45

50

The P inputs of which are the Start and Stop inputs of the device, respectively, the first key, the information input and the output of which are connected to the output of the clock generator and the counting input of the binary counter, respectively, the second key, the control input of which is connected to the inverse output of the first RS flip - ra, and the prohibition element, the output of which is connected to the clock input of the shift register, the inverse input of the prohibition element is connected to the input of the cipher block input, the element OR, the first input of which is the input Zero and the output is connected to the combined R-inputs of the shift register, the first RS flip-flop and the binary counter, connected in series to the first and last pulses selection unit, the input of which is connected to the output of the second key, and from the output of the specified block the last impulse of the series goes to the second the input of the OR element, and the first driver of the short front pulses, the output of which is connected to the inverse input of the BANNER element, the first driver of the short cut pulses, the input of which is combined with the input of the first generator a short front pulse generator, a second front pulse shaper, and a second short cut pulse shaper, the inputs of which are combined and connected to the output of the OR element, the third RS flip-flop, the S and R inputs of which are connected respectively to the outputs of the first shaper of short cut pulses and the second shaper of the front pulse, while the direct output of the third RS-flip-flop is connected to the synchronization input of the cipher block, the input of which is connected to the output of the second short pulse shaper slice, while the output of the higher bit shift register is connected to the information input of the inverter.

2. The device according to Clause 1, that is, in that the cipher input block contains, in each of the m channels, serially connected non-working clock cycles from the voltage generator, the RS flip-flop, the current sequence and the faulty output of my which is connected to the first situation, the second RS trigger is connected in series, B and

the input of the first element OR, the second input of which is connected to the inverse

five

five

0

0

five

Q

five

0

The P inputs of which are the Start and Stop inputs of the device, respectively, the first key, the information input and the output of which are connected to the output of the clock generator and the counting input of the binary counter, respectively, the second key, the control input of which is connected to the inverse output of the first RS flip - ra, and the prohibition element, the output of which is connected to the clock input of the shift register, the inverse input of the prohibition element is connected to the input of the cipher block input, the element OR, the first input of which is the input Zero and the output is connected to the combined R-inputs of the shift register, the first RS flip-flop and the binary counter, connected in series to the first and last pulses selection unit, the input of which is connected to the output of the second key, and from the output of the specified block the last impulse of the series goes to the second the input of the OR element, and the first driver of the short front pulses, the output of which is connected to the inverse input of the BANNER element, the first driver of the short cut pulses, the input of which is combined with the input of the first generator a short front pulse generator, a second front pulse shaper, and a second short cut pulse shaper, the inputs of which are combined and connected to the output of the OR element, the third RS flip-flop, the S and R inputs of which are connected respectively to the outputs of the first shaper of short cut pulses and the second shaper of the front pulse, while the direct output of the third RS-flip-flop is connected to the synchronization input of the cipher block, the input of which is connected to the output of the second short pulse shaper slice, while the output of the higher bit shift register is connected to the information input of the inverter.

2. The device according to Clause 1, which is designed so that the cipher input block contains in each of the m channels a voltage repeater connected in series, an RS flip-flop, the forward output of which is connected to the first

voltage torus, RS trigger, the direct output of which is connected to the first

the input of the first element OR, the second input of which is connected to the inverted output of the A8 flip-flop and to the first input of the first element AND, the second input of which is connected to the first input of the second OR element and to the S-input of the RS flip-flop, the R-input of which is connected to the second input the second element OR, whose upstream is connected to the first input of the second element AND, the second input of which is connected to the output of the first element OR, the third and fourth elements AND, the output of the first element AND is connected to the first input of the third element AND, and the output of the second

element AND is connected to the first input of the fourth element AND, while the clock inputs of the RS flip-flops of all channels are combined and are the input of the cipher input synchronization, the input is Read1, whose input is the combined second inputs of the third and fourth elements AND of all the channels whose outputs are respectively, the second and first outputs of the input block of the cipher, the input to which is reset are the combined inputs of the voltage repeaters of all channels.

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Claims (2)

Claim 1. A device for transmitting information by pseudo-random signals, containing a clock pulse generator, a binary counter connected in series, a code comparison unit and a first RS-trigger, an inverter unit and a trigger unit, the outputs of which are connected to the corresponding inputs of the inverter unit, the outputs of which are connected to the corresponding second inputs cod * comparison block, cipher input block, encoder, shift register and adder modulo two in series, the second input and output of which are connected respectively to volt each output and the information input of the shift register, the OR-HE element, the inputs of which are connected to the second outputs of the cipher input unit, an inverter whose control input is connected to the output of the OR-HE element, and the output is the output of the device, differing in TeM | that, in order to increase the speed and reliability of work by eliminating idle clock cycles from the generated sequence and faulty situations, the second RS-trigger, S- and The P. inputs of which are the Start and Stop inputs of the device, respectively, the first key, the information input and output of which is connected to the output of the clock and the counter input of the binary counter, respectively, the second key, the control input of which is connected to the inverse output of the first RS trigger, and The BAN element, the output of which is connected to the clock input of the shift register, the inverse input of the BAN element is connected to the input Read the cipher input block, the OR element, whose first input is the input and the output is connected to the combined R-inputs of the shift register, the first RS-flip-flop and the binary counter, series-connected block allocation of the first and last pulses of the series, the input of which is connected to the output of the second key, and from the output of the specified block, the last pulse of the series goes to the second the input of the OR element, and the first driver of short pulses of the front, the output of which is connected to the inverse input of the element FORBID, 'the first driver of short pulses of the cut, the input of which is combined with the input of the first driver short pulses of the front, the second driver of the short pulses of the front and the second driver of the short pulses of the cut, the inputs of which are combined and connected to the output of the OR element, the third RS-trigger, S- and R-inputs of which are connected respectively with the outputs of the first driver of the short pulses of the cut and the second driver short pulses of the front, while the direct output of the third RS-t Trigger is connected to the synchronization input of the cipher input unit, the Reset of which is connected to the output of the second short-pulse cutter, p In this case, the high-order output of the shift register is connected to the information input of the inverter. 2. The device according to claim 1, wherein the cipher input unit contains, in each of the w channels, a voltage follower, an RS trigger, whose direct output is connected to the first input of the first OR element, the second input of which is connected to the inverse 7th output of the RS trigger and to the first input of the first AND element, the second input of which is connected to the first input of the second OR element and to the S-input of the RS trigger, whose R input is connected to the second input of the second OR element, the output of which is connected to the first the input of the second element And the second whose input is connected to the output 10 of the first element OR, the third and fourth elements AND, the output of the first element And is connected to the first input of the third element And, and the output of the second element And is connected to the first input of the fourth element And, while the clock inputs are RS-triggers of all channels are combined and are the synchronization input of the cipher input block, the Reading input of which is the combined second inputs of the third and fourth elements AND of all channels whose outputs are the second and first outputs of the cipher input block, respectively '’reset which is the combined voltage follower inputs of all channels. Figure 2 I 392625 Fig.Z