SU590860A1 - Device for synchronization of pseudonoise signals - Google Patents

Description

one

The invention relates to radio engineering and can be used in receiving devices of radio communication systems.

A pseudo-noise signaling device is known, comprising a serially connected replicating unit and an inhibiting unit, the second input of which is connected to a time interval generator, the series-connected delaying unit, a clock selection unit, a shift register, an adder, a switch, the output of which is connected to the decision unit and the second input shift register, and the output of the prohibition block is connected to the corresponding inputs of the switch directly and through the load counter, the second input of which is connected n from the clock extracting unit, and the other output of the delay unit is connected to the other input of switch 1.

However, the known device is characterized by insufficient synchronization accuracy and high power consumption.

The purpose of the invention is to improve the timing accuracy and reduce power consumption.

To do this, a pseudo-noise signal-in synchronization device, containing a serially connected decisive unit and a prohibition unit, the second input of which is connected to a time interval generator, sequentially

the delay block, the clock selection block, the shift register, the adder, the switch, the output of which is connected to the decisive block and the second input of the shift register, the output of the prohibition block connected to the corresponding inputs of the switch directly and through the load counter, the second input of which is connected to the block clock selection and the other

the output of the delay unit is connected to another input of the switch, the matching element, the element NOT, the element AND and the execution counter are inputted in series, the second input of which is connected to the output

the clock selection unit and the output with the additional input of the switch, the output of the adder is connected to the input of the coincidence element, the output of which is connected to the third input of the execution counter, and the additional output of the switch is connected to the second input of the AND element, while the other output of the delay block is connected to the second input of the match item. The drawing shows a structural electrical circuit of the proposed device.

A device for synchronizing pseudo-noise signals contains a serially connected decision unit 1 and a prohibition unit 2, the second input of which is connected to a generator

3 time intervals, sequentially

connected delay block 4 ,, clock allocation block 5, shift register 6, adder 7, switch 8, the output of which is connected to the decision block 1 and the second input of shift register 6, and the output of block 2 of the ban is connected to the corresponding inputs of switch 8 directly and through a load counter 9, the second input of which is connected to a block 5 of the clock frequency, and another output of the delay block 4 is connected to another input of the switch 8, the matching element 10, the AND AND element, And 12 element and the executive the counter 13, the second input of which is connected to the output of the clock-selection unit 5, and the output to the additional input of the switch 8, the output of the adder 7 connected to the input of the coincidence element 10, the output of which is connected to the third input of the executive counter 13, and the additional output of the switch 8 connected to the second input of the element 12, while the other output of the delay unit 4 is connected to the second input of the matching element 10.

The device works as follows.

At the initial moment of time at the output of decisive unit 1 there will be a low voltage level, therefore the first impulse of the generator 3 time intervals passes through the prohibition unit 2 and sets the trigger 14 and the control trigger 15 to the zero state and resets the load counter 9 and the execution counter 13 . Since the trigger 15 is in the "O" state, the input signal is through the delay unit 4, the valve 16 and the OR element 17 is fed to the input of the shift register 6. The clock pulses from the clock extracting unit 5 receive the pseudo-noise signal symbols advancing into the shift register 6. The capacity of the load counter 9 is equal to the number of bits of the shift register 6, so when the first written character in the shift register 6 reaches the last bit, an overflow signal appears at the output of the load counter 9. This signal transfers trigger 14 to the state "1. The signal "1 from the trigger 14 is fed to the input element And 12 and the Executive counter 13 will be open for counting clock pulses, if the symbols of the pseudo-noise signal at the output of the adder 7 and the output of the block 4 delay. If the characters do not match, then with the help of the element NOT 11 and the element And 12 a pulse of resetting the actuating counter 13 to the zero state will be formed. This impulse is generated as follows.

At the output of the coincidence element 10, the signal "O" is generated, if the Pseudo-Ps signal symbols on both inputs of the coincidence element 10 are of the same level. If the pulses at the output of element 10 coincide, a signal "1 is formed, and on the output of element 11, there will be a signal" O, which, through element 12, resets the actuating counter 13, the number of bits of which is determined based on the requirement of the recurrent equations logs (+1) - If K of the recurrent equations is satisfied for the received signal symbols, then executive counter 13 counts K of clock pulses and the output of the signal is "1, which

arrives at the input of the element 18 of the switch 8 and generates at its output a signal "1, which transfers the control trigger 15 to the state" 1. Valve 16 and O1 then close; valve closes

19. Next, the shift register 6 receives the characters from the output of the adder 7, i.e. the reversing loop of the shift register 6 closes and a reference signal begins to be generated, which is compared with

signal in the decision block 1. If the phases of the pseudo-noise signal being formed and received coincide, the output of the decision block 1 shows a signal that prevents the generator from passing 3 time intervals and the device will be in autonomous mode. If the phases of the signals do not coincide, pa of the output of the decision block 1 of the signal pet and the second pulse from the generator of 3 time intervals through

The prohibition unit 2 switches the device to the recording mode of the received signals in the shift register 6, and the process described above is repeated. The proposed device compared to

known has more accurate synchronization and lower power consumption.

Claims (1)

Invention Formula Device sync pseudo noise signals, containing a serially connected decision unit and a prohibition unit, the second input of which is connected to a time interval generator, a serially connected delay unit, an allocation unit clock frequency, shift register, adder, switch, the output of which is connected to the decisive block m. and the second input of the shift register, and the output of the prohibition block is connected with the corresponding switch inputs directly and via a load counter, the second input of which is connected to the clock selection unit, and the other output of the delay unit is connected to another input of the switch, characterized in that in order to improve synchronization accuracy and reduce power consumption, successively offset elements, the element NOT, the element AND the execution counter, whose second input is connected to the output of the clock selection unit and the output to the additional input of the switch, are entered, and the output of the adder is connected to the input of the match element, the output of which Comm I1011 with the third input counter, and the auxiliary output of the switch is connected to the second input of the And element, while another output of the delay unit is connected to the second input of the matching element. Sources of information taken into account in the examination 1. USSR author's certificate №374594, M. Kl.2 G 06F 5/06, 1970.