SU1356251A1 - Device for separating cycle synchronization signal - Google Patents

Abstract

The invention relates to telecommunications and improves speed. The device contains a strobe block 1, a clock synchronization block 2, a shift register 3, a NOT 4 and 5 zl-t, an AND 6 - 8 zl-t, an EL OR 9 unit. 1 Il. oo ate O5 N3 SP

Description

The invention relates to telecommunications and can be used in discrete message transmission systems for implementing frame synchronization.

The purpose of the invention is to increase speed,

The drawing shows a structured electrical circuit of the sync signal extraction device.

The cyclic sync signal extraction device contains a strobe unit 1, a clock synchronization unit 2, a shift register 3, the first and second elements are NOT 4 and 5, the first is the third element AND 6-8, the element OR 9.

The cyclic sync signaling device operates as follows.

Each n-bit cycle of the transmitted (in the absence of interference and received) message contains K information bits and one synchronizing bit. The location of this bit is determined on the receiving side by examining the correlation dependence between the sync signal and the information bits of the message. The randomness factor that occurs during the transmission of the information part of a message results in a random distribution of ones and zeros in the transmitted message cycles, while the input clock signal has a continuous repetition at one point of the cycle. This repeatability indicates the boundary (beginning or end) of the message cycle. The repeatability of the sync signal in the cyclic sync selector is determined by continuous sequential analysis of the received information (input signal),

At the initial moment in the register 3 there is no information, as a result of which O are present at its outputs. Therefore, the output of the second element is NOT 5 and the output of the first element is NOT 4 and the levels 1 are formed. For this reason, the first pulse generated at the additional output of the clock synchronization unit 2, passes to the output of the third element And 8 (the second element And 7 is closed at the first input by zero voltage from the output of the first discharge of the register 3) and further to the output of the device for extracting the cycle sync signal and the setting input

0

five

0

five

0

five

0

five

0

five

register 3, as a result of which units are written in all its bits. In this way, the frame alignment device is prepared to look for the clock signal.

The input signal (received message elements) is fed to the information input of the strobe unit 1 and the input of the clock synchronization unit 2, the outputs of which generate clock pulses, synchronous and common-mode message elements. The gate unit 1 determines the value (single or zero) of each of the received message elements and generates output pulses in the case of receiving message message elements. Under the action of the clock pulses from the output of the clock synchronization block 2, information is promoted in register 3. The information from the output of the last bit of register 3 is fed to the second input of the first element 6 (in the first cycle of operation of the device for extracting the frame sync signal is n single pulses) the first input of which comes from the output of the strobe unit 1 pulses corresponding in time to the arrival of the message elements (input signal). The first element 6 performs the logical multiplication of the information arriving at its first and second inputs, as a result of which register 3 records the unit to the corresponding bit only with simultaneous input of level signals to the first and second inputs of the first element 6 (by the end the first cycle of operation of the device for extracting the cyclic clock signal; the information in the register 3 corresponds to the first elements of the input signal). In the second and subsequent cycles of the operation of the cycle sync selection device, sequential logical multiplication of information bits received in a given message transmission cycle is performed by the corresponding bits of the analysis result obtained from the previous transmission cycle.

The random alternation of information units and zeros in each information bit of received cycles and the continuous arrival of a sync signal (for example, a single bit) in each cycle result in

at one point in time in register 3, the recorded combination IOO ... O appears. A single signal level from the output of the first bit of the register 3 prepares the second element AND 7 for operation on the third input. Zero signal levels from the outputs of the bits (from the second to the last) register 3 arrive at the element OR 9, as a result of which the output of the first element is NOT 4, a single signal level is formed, which prepares the second element AND 7 for operation on the second input. Since the second and third inputs of the second element And 7 present a single signal level (the third element And 8 at this time is closed on the first input of the zero level m second output signal of the NOR 5), the pulse generated at the output of block 2 additional clock passes to the output of the second AND gate 7 (and additional output of frame sync signal separating device), indicating that the allocation of the input clock signal.

Since in register 3 the combination 100. ,, O is written, and the synchronizing unit arrives in each message cycle, the period of formation of signals at the additional output of the device for extracting the cycle sync signal is equal to the duration of the cycle of received messages

In the case of a distortion of the synchronization unit (due to interference in one of the cycles of received messages, register 3 contains the recorded combination 000, .. Oh. As a result, at the output of the second element HE 5 and the output of the first element HE 4, single signal levels are formed, preparing the third element And 8 (the second element And 7 at this time is closed at the third input by the zero level of the signal from the output of the first discharge of the register 3), and therefore, the pulse formed at the additional output of the block 2 clock synchronization, Odita on the output of the third AND gate 8, and further

BNIIPI

Order 5814/56 Edition 636

Random polygons pr-tie, Uzhgorod, st. Project, 4

562514,

the output of the frame alignment device and the setup input of the register 3, writing units to all of its bits. The cyclic signal allocation unit is prepared for the sync signal search process. Further, the operation of the frame alignment selection device is carried out similarly to that described.

ten

Claims (1)

Invention Formula A cyclic sync signal separator comprising serially connected clock synchronization unit and shift register, serially connected strobe unit and first AND element, as well as OR element, second AND element and third And element, whose output is connected with a setting input of the shift register, clock synchronization block output connected to the clock input of the gating unit, and the combined information input of the gating unit and the input of the clock, synchronization and output of the third element ts, respectively, the input and output of the device, about tl and so that, in order to improve speed, the first and second elements are NOT introduced into it, and the additional output of the clock synchronization unit is connected to the first inputs of the second and third elements, the second inputs of which connected to the output of the first element is NOT, the third input of the second element is AND is combined with the input of the second element is NOT and connected to the output of the first bit of the shift register, whose information input is connected to the output of the first element AND, the second input is cat It is combined with the input of the OR element and connected to the output of the last bit of the shift register, the other outputs of which bits are connected to the corresponding other inputs of the OR element, and the third input of the third element AND and the input of the first element are NOT connected respectively to the outputs of the second element NOT and element OR, and the output of the second element AND is an additional output device Subscription