SU915265A1 - D-sequence discriminating device - Google Patents

Description

The invention relates to radio engineering and can be used in radio communication and radar systems.

A device for extracting a D-sequence containing a discriminator connected in series, a low-pass filter, a generator (voltage controlled, and a frequency divider) is known, while the discriminator input through a serially connected correlator, threshold unit, control unit and D-code generator is connected to the first the input of the modulo two, while the output of the generator, voltage controlled, is connected to the auxiliary input of the generator D-code [1].

However, in the known device requires considerable time to search for the D-sequence.

The purpose of the invention is to increase the speed of the device.

This goal is achieved by the fact that in the device for the selection

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D-sequences containing (serially connected discriminator, low-pass filter, voltage controlled oscillator and frequency divider, while the discriminator input through serially connected correlator, threshold block, control unit and D-code generator is connected to the first input of the modulo two , while the output of the voltage controlled oscillator is connected to the auxiliary input of the D-code generator, a clock extraction unit, an additional frequency divider and a noise supporter unit are introduced Signals (BSS), the first input of which is connected to the D-code generator output, the second input is combined with the frequency divider and the additional frequency divider input, the output of which is connected to the third input of the CAS formation unit, the fourth input of which is connected to the output of the threshold block, and

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the fifth input is combined with the input of the correlator and the input of the sync signal extraction unit, the output of which is connected to the second input of the control unit, the output of the adder modulo 2 is connected to the auxiliary input of the correlator and the auxiliary input of the discriminator, the first is connected to the second input of the modulator two the output of the block 10 forming the PSS, the second output of which is connected to the third input of the modulo two.

At the same time, the block forming the PSS П contains n - 2 chains (where η = 3, 15

4, 5, ...), each of which contains a series-connected multiplier, a filter, a clock extraction unit, a switch and a D-code generator, the output of each of which is bottom is connected to the first input of the multiplier of the subsequent circuit and is the first output of the forming unit PSS, the filter output of each circuit is connected to the second multiplier input of the subsequent circuit, and the second inputs of the switches of each circuit are combined and are the fourth input of the PSS forming unit, while the second "inputs of the D-code generator are connected to s zo respective frequency dividers which are respectively second and third inputs PNS forming unit, a first input of multiplier first input of the first circuit ₃₅ Bloch ka forming PNS and its second input is the fifth input 'forming unit PNS.

FIG. 1 shows a block diagram of the proposed device ’, FIG. 2 - block diagram of the block forming the PSS.

The device for selecting the D-sequence contains a discriminator 1, a low-pass filter 2, a voltage controlled oscillator 3, a frequency divider 4, a correlator 5, a threshold unit 6, a control unit 7 and a D-code generator 8, an adder 9 modulo two, 10 sync signal extraction, additional divider 11 frequencies and block 12 of the formation of PSS.

The block 12 forming the PSS contains ⁵⁵ p-2 circuits (where η = 3, 4, 5, ...), each of which contains a multiplier 13, a filter 14, a block 15 for extracting a clock signal, a switch 16 and a generator. 17 D-code.

The device works as follows.

If the signals at the input and output of the device do not match in shape, then there is no voltage at the output of the threshold unit 6.

Through the control unit 7 to the input of the generator 8 D-code signals come, setting the initial state of the generator 8 D-code.

The period of the sync signals (sync video pulses) is 4 where is the sampling duration of the input D-sequence. The sync signals are generated in the block 10 of the sync signal.

The sync signal extraction unit 10 includes a multiplier, a delay line for a time equal to the sampling duration, a bandpass filter and a shaper of short video pulses. These short video pulses are tied to the specified points of the sinusoid at the output of the bandpass filter. Video signals are also fed to the input of the generator 17 D-code and to the input of the generator 17 'D-code. They are produced at the inputs of the blocks 15 and 15 'of the selection of the sync signals, are tied to the given points of the sinusoids at the outputs of the bandpass filters contained in the blocks 15 and 15', and have periods equal to 8T _And 16TG _And, respectively.

To the additional input of the generator 8 D-code from the output of the generator 3, voltage controlled, receives the triggering clock video signals with a period.

The second input of the 17 D-code generator from the output of the 4 frequency divider receives trigger pulses with a period of E'S'i, and the second input of the 17 D-code generator - pulses with a period of 4 and.

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At the outputs of identical generators 8, 17, and 17 ', D-codes are generated with periods DTC, S'Ci and 16 Gy, and a sampling duration of 2TcI 4 ^.

These D-codes are then summed modulo two in adder 9.

This sequence is formed at the output of the adder 9 modulo two when applying to it three D-after, with a period of 4,

8Hz t 16G _And . After the end of the first

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the synchronization stage 'reference D-sequence at the output of the adder 9 modulo two coincides with the received D-sequence. The voltage at the output of the correlator is 5 max-5 but. At the output of the threshold block 6, a signal appears that takes the control block 7 and the circuit switches to the positions at which the D-code generator 8 input disconnects ¹⁰ from the output of the syncro- ⁴ signal extraction block 10, and the D-code generators inputs of the ShPS 12 circuit from the outputs of the block sync signals. At this point, the first synchronization stage ends- <5.

At the second synchronization stage, in the tracking mode for the delay of the received D-sequence, the phase of the voltage at the output of the generator 3, controlled by the voltage, varies depending on the time error между between the reference and the received-sequences. This allows ’to combine with high accuracy the position of the reference D-sequence with the received D-sequence.

The time it takes to synchronize a device is small, determined by the ₃ θ is divided by the duration of the transient process in this device and is comparable to the duration of one period of the input D-sequence.

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Claims (2)

Claim 1. A device for isolating the D-sequence, comprising series-connected discriminator lowpass filter ^40, a voltage controlled oscillator, and a frequency divider, with the input of the discriminator via series connected correlator, the threshold unit, a controlled Lenia ⁴⁵ and the D-code generator connected to the first input modulo two, while the output of the generator, voltage controlled, is connected to the auxiliary input of the generator ⁵⁰ D-code, characterized in that, in order to improve speed. introduced a sync signal extraction unit, an additional frequency divider and a noise-like signal shaping unit (PSS), the first input of which is connected to the output of the D-code generator, the second input is combined with the output of the frequency divider and the input of the additional frequency divider, whose output is connected to the third input of the unit forming the PSS, the fourth input of which is connected to the output of the threshold unit, and the fifth input is combined with the input of the correlator and the input of the sync signal extraction unit, the output of which is connected to the second input of the control unit phenomenon, where the output of the modulo two adder is coupled to an additional input of the correlator and the additional input of the discriminator, a second input of the modulo two adder output is connected first PNS forming unit, the second output of which is connected to the third input of the adder of modulo two. 2, The device according to claim 1, which is based on the fact that, the block forming the PSS contains p-2 circuits (where l = 3, 4, 5,. ·.), Each of which contains serially connected multiplier, filter, block sync signal extraction, D-code switch and D-code generator, the output of each of which is connected to the first input of the multiplier after the chain and is the first output of the PSS formation unit, the output of the filter of each circuit is connected to the second input of the multiplier of the subsequent circuit combined and are the fourth in house of the block forming the PSS, while the second inputs of the generator of the PSS forming unit, the first input of the multiplier of the first circuit is the first input of the block forming the PSS, and its second input is the fifth input connected to the second inputs of the generator. block forming the PSS. Sources: information taken into account in the examination 1. USSR author's certificate -Ν ’553753, cl. H 04 ί 7/02, 1977 (prototype). 55 915265 doc / chd FIG. one 915265 Phi 1.2.