SU819980A1 - Synchronizing device - Google Patents

Description

shift, converter 7, frequency divider 8, control element 9, auto-oscillator 10 and analyzer 11 false sync pulses, consisting of And 12, scrambler 13, And block 14, and trigger 15.

The synchronization device operates as follows.

The pulses from the output of the selector 1 are fed to the input of the analyzer 11, which, according to a predetermined program, passes the sync pulses to the input of line 3 and register 6.

The principle of operation of the Analyzer 11 is based on the fact that the frequency of following the clock pulses and the range of its possible changes are known. Therefore, the analyzer 11 can be performed on the basis of a periodic signal generator synchronized by clock pulses.

As a periodic signal generator, a scrambler 13 is used, the phasing of the frequency of the following pulse combinations is carried out by clock pulses, and the moments of resolution and prohibition of the passage of clock pulses to the input of line 3 and register 6 are determined by block 14, which recognizes two combinations of cell scrambler register 13, one of which a sync pulse appears, and a friend is formed in the scrambler register 13 after the sync pulse appears. Block 14 through the trigger 15 allows or prohibits the passage of clock pulses through the element 12.

As the clock pulses of the scrambler register 13, pulses of the auto-oscillator 10 are used.

The sync pulses passing through the analyzer 11 are fed to the register 6 to set its cells to their initial state, and through line 3 to the input of the phase discriminator 4. To the other input of the phase discriminator 4 through the divider 8 and the former 2, pulses are output from the output of the autogenerator 10 As a result of the signals applied to the inputs, a pulse appears at the output of phase discriminator 4, the law of changing the duration of which reflects the ratio of clock frequency and pulse output of the oscillator 10. Pulse From the output of the phase discriminator 4 is recorded in register b, the recording is carried out after setting the register b to its initial state and lasts for the duration of the recorded pulse, which is achieved by applying pulses from the output of the autogenerator 10 (used as clock pulses) to the synchronization input register cells 6 through element 5, to one input of which pulses are output from the oscillator 10, and to the other input to pulses from the second output of phase discriminator 4.

The law of displacement in the register of 6 neighboring cells in opposite states, when considering this movement at the moments of arrival of clock pulses, strictly corresponds to the law of change in the duration of the pulse recorded in register 6, i.e. the law of change in the ratio of the frequencies of clock pulses and pulses generated at the output autogenerator 10. The outputs of all the cells of the register 6 are connected to a converter 7, which provides a change in the magnitude of the DC voltage at the output according to the law of a change in the pulse duration on you phase discriminator 4.

Divider 8 and driver 2 are designed to generate pulses applied to the input of phase discriminator 4 with a tracking period not exceeding the delay time of register 6. In addition, divider 8 is designed to obtain the clock frequency used in the scrambler register 13.

An introduction to the proposed device for forced synchronization of the analyzer 1 1 effectively solves such mutually contradictory issues as the provision of high noise immunity of the clock selection circuits and the elimination of the impact on the devices for forced synchronization of spurious clock pulses.

Claims (2)

1. A synchronization device comprising a clock selector, a serially connected delay line and a phase discriminator and a serially connected control element, an auto-oscillator and a frequency divider characterized by In order to improve noise immunity and speed, a false clock analyzer, serially connected elements AND, shift register and converter, as well as a pulse shaper were introduced, while the output of the clock selector is connected to the input of the delay line and to the corresponding input of the shift register through the analyzer false sync pulses, to the control input of which an additional output of a frequency divider is connected, the output of which is connected to another input of the phase through a pulse shaper discriminator outputs of which are respectively connected to the control input of the shift register and to the first input of the AND gate, the second The input of which is connected to the output of the autogenerator, and the output of the transformer is connected to the input of the control element. 2. The device according to claim 1, characterized in that the false clock pulse analyzer is made in the form of an AND element combined with a scrambler, the outputs of which are connected to the trigger inputs through an element block AND connected to the control input of the element AND the output is the output of a false clock analyzer. Sources of information taken into account in the examination I USSR Author's Certificate No. 534883, cl. H 04 N 5/04, 1977 (prototype).