SU1487192A1 - Code-to-pulse-repetition rate converter - Google Patents

Description

The invention relates to computing and can be used in control devices.

as a programmable unit of time intervals in the formation of input effects on the controlled object. The purpose of the invention is improving the accuracy of conversion in a wide range of period formation. The converter contains

The invention relates to a pulse and computing technology and is intended for use in test equipment as a programmable unit of time intervals for the test object.

The purpose of the invention is to improve the accuracy of the conversion in a wide range of formation of the period.

FIG. 1 shows a functional code converter circuit during a pulse repetition period; in fig. 2 example of implementation of a program block, a shift register and a multi-generator of the reference frequency, a shift register, two multiplexers, a pulse counter, a memory block, a four-trigger, two OR elements, a key, a trigger pulse driver, performed on two C-triggers and two NAND elements , program block and output bus. Period formation is carried out by counting by the pulse counter the number of pulses produced by the reference frequency generator, while eliminating the influence of the counter switching delays on the conversion accuracy, first, by eliminating the counter from the process of forming the period corresponding to the lowest times. rows of code specified by the software block, and secondly, by ensuring that the counter runs ahead in the formation of the remaining portion of the period. 2 hp f.ly, 3 il.

plexors in their relationship; in fig. 3 - timing charts of the device.

The code converter in the pulse repetition period (Fig. 1) contains the reference frequency generator 1, shift register 2, multiplexers 3,4, counter 5 pulses, memory block 6, triggers 7-10, elements OR 11,12, key 13, driver 14 trigger pulses, consisting of two L-triggers 15,16, two elements AND-NOT 17,18 and bus 19 "Start", program block 20 and output bus 21.

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Shaper 14 trigger pulses contains two три-trigger 15, 16, forming in the aggregate a two-bit shift register, two elements AND NOT 17.18 and bus 19 "Start".

Program block 20 (Fig. 2) is designed to store information about the values of the lower and higher digits of the codes of the formed time interval and transmit this information to multiplexers 3,4 and memory block 6, as well as to generate signals controlling the operation of the trigger 8. Program block 20 ( figure 2) contains registers 22, 23, used for storing the lower and higher digits of codes, the element 24 of the switch 25, performed on the software switches and buttons.

The operation of the code converter during the pulse repetition period is as follows.

Let, for example, it is necessary to form a repetition period of 5 μs -565 ns at a generator frequency £ _op = 200 MHz. Using the switch 25 of the program block 20, the operator writes to registers 22,

23 information on the values of the lower and upper digits of the codes of the formed time interval. The codes are divided into lower and higher digits based on the discreteness of programming determined by the period T _op of the reference frequency generator 1 (in our case T _ohm = 5 ns), the width of the shift register 2 (in our case, a 10-bit ring shift register covering conversion range equal to the time interval of 5 ns-10 = = 50 ns), as well as the duration of the time interval being formed. In this example, when forming a time interval of 5 μs 565 ns, the low-order code is 3, and the high-order code is 111. The 3 low-order code, corresponding to the binary system with the sum of 2.2, converts a portion of the time interval equal to 5 ns * ¹ . <3 = 15 ns, and what the 111 most significant digits corresponding to the binary system the sum of the numbers 2 °, 2 ', 2, 2, 2 ^? , ^2nd , provides a time interval (taking into account the conversion range of the shift register 2), equal to 50 ns-111 = 5550 nm,

₍ as a result, the total time interval being formed will be 15 ns + 5550 ns = 5565 ns, i.e.

5 μs 565 ns.

Thus, the programs specified by block 20, code 3 low bits and code 11.1 high bits correspond to the considered example of conversion of a period of 5 μs 565 ns. By the signal of the end of recording information about the code value of the generated time interval corresponding to the high bits of the code, C - trigger input 8 receives "1", which sets it to the state "1" through the direct output, and the memory cell of block 6 also records "1" corresponding to the code 111 address. Signal "1" from the direct output of the trigger 8 goes to the control input of the multiplex xor 3, allowing passage through it of the signal from the high-order output of the shift register 2. Signal "0" from the inverse output of the trigger 8 allows the trigger 9, 10 and the passage of the signal from trigger 7 to the shift register 2 through the key 1-3.

But the “Start” signal and the arrival of a clock pulse at the inputs ϋ of the trigger 15 of the driver 14 of trigger pulses (Fig. A, b), respectively, the time T (), the state of the trigger 15 changes, at which the direct output is set to 0 ", and inverse" 1 "(Fig. 3, at time point C ₂ ). Similarly, on arrival at the inputs of the три-flip-flop 16 of the signal "1" and the next clock pulse, the output state of the flip-flop 16 changes, and its output is set to "1" (Fig ·, Зг, time s. ^), Signals with output O -triggers 15,16 arrive at the combined inputs of the elements AND-NOT 17,18, resulting in their outputs, which are the outputs of the driver 14 trigger pulse, a pulse is formed, the duration of which is equal to the period T of the pulse generator 1 reference frequency (Fig. RE) , Impulse from the output of the element AND-NOT 18 enters cut the element OR 11 to the ϋ-input of the trigger 7, to the synchronization input of which the pulses pass from the generator 1 of the reference frequency. At the exit trig—

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ι-er 7, the first output impulse is formed, the duration of which is equal to the period T (fig, Ze, moment of time

. This pulse arrives at the inputs of counter 5, triggers 9, 10 and key 13 o. At the same time, the output of counter 5 sets the address of the first cell of memory block 6 (FIG. 3), triggers 9, 10 change their state 10 (FIG. 3), prohibiting passing signals through multiplexer 4, and through the key 13 the first pulse arrives at the control input of the shift register 2, as a result of which the last 15 starts its work in the ring and pulses shifted relative to each other are formed at its outputs (Fig. 3k-1k10 ). The resolution signal from trigger 8 through multi- 20 plexer 3 to trigger 10 passes a signal from the output of the high-order shift register 2, the arrival of which is a trigger. 10 changes its state to "1" (Fig. Zi, moment 25

time C ^) “At the same time, the signal from the output of multiplexer 3 through the element OR 12 arrives at the input of the shift register 2, which from the moment of time forms shifted zo impulses in the new working ring (FIG. 3 k1-k10). Upon arrival of the signal "1" from trigger 10 to the input of multiplexer 4, the output signal from the third to the 10th digit of the shift register 2 corresponding to the code 3 lower bits of the input code is fed through multiplexer 4 to the inputs of counter 5 and trigger 9. At the same time, the counter 5 changes, in accordance with what the selection of the cells of the memory block 6 takes place (Fig. W, W, W, Mo-> ment of time s ^). The output information from the memory unit 6 is fed to the second input of the trigger 9, which prohibits the passage of signals from the outputs of the shift register 2 through multiplexer 4 and the element OR 11 to the output trigger 7. The above described operation cycle

repeats until you

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during the course of counter 5, the code of the cell address of the memory block 6 corresponding to the code of the most significant digits is not established, i.e., in our case, the code 111.

Upon reaching the specified code

55

counter 5 at time point C ₇ , information is changed in memory block 6 (Fig. ZJ) and trigger 9 is switched when it arrives at

the first input of the signal from the first output of the multiplexer 4 (fig. Zl).

The output of the trigger 9 and, therefore, the fourth input of the multiplexer 4 sets the signal "1", allowing the passage of signals from the outputs of the digits of the shift register 2 through the multiplexer 4 and element 11 to the output trigger 7, At the time of the output of the trigger 7 a second output pulse is formed (Fig. Ze),

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Thus, the formation of a pulse repetition period. In this case, the counter, which introduces the main part of the error in the conversion process, is excluded from the process of forming a period section proportional to the low bits of the input code. This function is assigned to the shift register, whose work is organized in a ring mode. Elimination of the counter (partial) makes it possible to reduce the number of its discharges (by the number of low-order digits), resulting in the possibility of increasing the operating frequency of the reference frequency generator, which, in turn, increases the accuracy of conversion in a wide conversion range,

Claims (3)

Claim 1, a code converter in a pulse repetition period, containing a reference frequency generator, the output of which is connected to the synchronization input of the first trigger, whose information input is connected to the output of the OR element, and a pulse counter, to increase the accuracy of conversion to wide the period formation range, a shift register, a program block, the first and second multiplexers, a memory block, the second, third and fourth triggers, the second OR element, the key and the impulse trigger generator are introduced into it owls, the input of which is combined with the first input shift register and is connected to the output of the reference oscillator, a first output connected to a second input of the shift register, the third input of which is connected to the output of the second OR gate having a first input coupled to a second vyΙάΒ the driver of the trigger pulses, and the second input is combined with the synchronization input of the fourth trigger and connected to the output of the first multiplexer, the first control inputs of which are combined with the corresponding first control inputs of the second multiplexer and connected to the first outputs of the program block, the second outputs of which are respectively connected to the information inputs of the block memory, and the third and fourth outputs are respectively connected to the information input and the synchronization input of the second trigger, direct in the stroke of which is connected to the second control input of the first multiplexer, the information inputs of which are combined with the corresponding information inputs of the second multiplexer and connected to the outputs of the shift register, the fourth input of which is connected to the key stroke, the first input of which is combined with the setup input of the third trigger and the reset input the fourth trigger and is connected to the inverse output of the second trigger, and the second key input is combined with the reset inputs of the pulse counter and the third trigger, the input is set the fourth, trigger, is connected to the output of the first trigger and is the output bus, while the counting input of the pulse counter is combined with the synchronization input of the third trigger and connected to the first output of the second multiplexer, the second and third control inputs of which are respectively connected to the outputs of the third and fourth triggers and the second output is connected to the first input of the first OR element, the second input of which is connected to the third output of the driver of trigger pulses, and the outputs of the pulse counter are connected to address input2 3 tribute to the memory block whose output connected to the information input third trigger. 2 "Converter according to claim 1, which is based on the fact that the driver of the triggering pulses is made on two ϋ-triggers and two AND-NOT elements, the first inputs of which are combined, are connected to the direct output of the first 13-trigger and are the first output of the driver of the triggering pulses, the second and third outputs of which are the outputs of the first and second elements AND — NOT, respectively, the second inputs of which are combined and connected to the output of the second три-flip-flop, the 0-input of which is connected to the inverse output of the first 13-flip-flop, the ϋ-input of which is Xia tire "Start", and the C-input is combined with the C-input of the second ϋ-flop and is the input trigger pulse shaper, 3, the Converter according to claim 1, o t - kicking the fact that the program block is executed on the switch, the element And the first and second registers, the outputs of which are respectively the first and second outputs of the program block, the third output of which is the output of the element I. the second, inputs: which are connected to the corresponding outputs of the second register, the synchronization input of which is connected to the first output of the switch and is the fourth output of the program block; the second output of the switch is connected to the synchronization input and the first register, the information inputs of which are combined with the corresponding first information inputs of the second register and connected to the third outputs of the switch, the fourth outputs of which are connected to the corresponding second information inputs of the second register. 1487192 fir. 2 1487192 "S Cha * sa © aas x 5: H