SU1487153A1 - Pseudorandom number generator - Google Patents

Description

The invention relates to a pulse technique. The purpose of the invention is the extension of functionality due to the generation of "-bit non-correlated pseudo-random numbers - achieved by the introduction of register 9, multiplexer 11 and counter 13 pulses. The generator also contains a generator of 1 clock pulses, G-trigger 2, element I 3, switch 4, counter 5 pulses, adder 6, element OR 7, block 8 of memory, adder 10 modulo two, £) -trigger 12. 1 ill.

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The invention relates to a pulse technique and can be used in computing and information and measuring equipment.

The goal of the theory is to expand the functionality of a pseudo-random number generator by generating “-bit non-correlated pseudo-random numbers.

The drawing shows a structural diagram of a pseudo-random number generator.

The pseudo-random number generator contains a clock pulse generator 1, the output of which is connected to the input of the Τ'-flip-flop 2 and the first input of the element 3, the output of which is connected to the input of the switch 4, the first pulse counter 5, the outputs of which are connected to the first group of inputs of the adder 6, the element OR 7, the output of which is connected to the control input of the memory block 8, the outputs of which are connected to the corresponding inputs of the register 9, the corresponding output of which is connected to the second input of the adder 10 modulo two, multiplexer 11, the output of which dinene with information input £> -trigger 12, the installation of which is connected to the output of the second counter 13 pulses, the synchronization input of which is connected to the output of the first counter of 5 pulses, the synchronization input of which is connected to the synchronization input of the register 9, with the second input of the element OR 7 and c the first output of the G-flip-flop 2, the second output of which is connected to the second input of the element I 3, the output of which is connected to the first input of the element OR 7 and to the synchronization input of the ΰ-flip-flop 12, the output of which is connected by the first input of the adder 10 modulo two, the output of which is connected to the first information input of the memory block 8, the outputs of which are connected to the corresponding information inputs of the multiplexer 11, the control inputs of which are connected to the corresponding outputs of the second group of outputs of the switch 4, the first group of outputs of which are connected to the second group of inputs of the adder b, outputs which is connected to the corresponding address inputs of the memory block 8. The installation input of the second counter 13 pulses is connected to the corresponding output of register 9, the Ζth output of which is connected to (r + 1) -th input (/==.1, 2, ..., n — 1) of memory block 8. The group 14 of the inputs of the switch 4 are the control inputs of the pseudo-random number generator.

The device works as follows.

The signal from the output of the generator 1 clock pulses fed to the input of the G-trigger 2 and the first input element And 3. On the first and second outputs of the G-trigger 2, signals are generated that are offset in time. Positive pulse at the output of the element And 3

formed at the time of the impact of the clock pulse in the presence of a positive signal at the second output of the 7'-trigger 2.

The pulse coming from the first output of the G-flip-flop 2 to the synchronization input of the first counter of 5 pulses increases by one the code M at its outputs connected to the first group of inputs (first term) of the adder 6. When the control input 4 is affected by the control signal from the element output TH 3 to the inputs of the second group of inputs (second term) of the adder 6 and the control inputs of the multiplexer 11 serves zero code combinations. In this case, the code M is formed at the address inputs of the memory block 8, which determines the address of the polled memory cell. The mode of operation of memory block 8, the number of addressable "-bit memory cells of which is equal to the number / e = 2" ^{1 of the} state of the first counter 5 pulses, is set by a signal at its control input. With a single signal, the binary code combination contained in the cell with the address Λ4 is read , from the inputs of register 9, in which this combination is rewritten by a pulse from the first output of the G-trigger 2. Therefore, in the first cycle of operation, a binary code signal is generated at the outputs of the device, equal to the content of the polled cell of the 8th block memory. The signal output from the corresponding, e.g., the last digit of register 9 is supplied to the second input of the adder 10 and modulo two to the input of setting the second counter 13 pulses. In the case of a single signal the contents of the second counter 13 becomes zero pulses.

With the arrival of the next clock pulse from the output of the clock generator 1, the G-trigger 2 goes to the zero state and the switch 4 connects to the second group of inputs of the adder b and the control inputs of the multiplexer 11 binary code combinations from the group 14 of the control inputs of the device. At the address inputs of memory 8, a new binary code signal is generated, which determines the address of the new polled “-bit memory cell, the binary combination from the outputs of which is bitwise fed to the information inputs of the multiplexer 11. The output from the discharge of memory 8 under the number, determined by the value of the binary code combination on the control inputs from the second group of outputs of the switch 4. A pulse from the output of the element And 3 this signal is recorded P-trigger 12 and enters the first in stroke of modulator 10 modulo two. At the end of the pulse from the output of the element And 3 switch 4 again connects to the second group of inputs (second term) of the adder 6 a zero code signal, which ensures the formation of address 1487153

the inputs of block 8 of the memory of the binary code combination M equal to the contents of the first counter of 5 pulses. At the same time, the zero signal from the output of the element OR 7 at the control input of the memory block 8 transfers it to the information recording mode from its information inputs. At this point, the first information input of memory block 8 contains a signal equal to the result of modulo-summing two signals from the output of the corresponding, for example, the last digit of register 9 and the signal from the output of the O-flip-flop 12. At the same time, n — 1 most significant bits of the information inputs of the block 8 memory number is formed, which is a shift to the previous contents of the cell with the address M by one digit to the right. The zero signal from the output of the element OR 7 is written to the cell with the address M, on which the device operation cycle ends.

Similarly, the first counter of 5 pulses passes through all 2 ^{tons of} states, ensuring that all “-bit cells of memory block 8 are addressed sequentially. After 2 "'cycles of operation, the contents of the first counter of 5 pulses will again take the value M and a binary code combination will be formed at the outputs of the device, previously recorded in the memory cell with the given address as a result of modulo two and shift by digit to the right. After another 2 ^t cycles of the device number at its outputs will be shifted relative to the initial two digits to the right and so on.

As a result, the operation of memory block 8 in conjunction with register 9 is similar to the functioning of the “^“ - bit shift register covered modulo two feedback. Under the condition 6 = 2 ">" the numbers generated in the bits of register 9 and output to the output device are pseudo-random and uncorrelated .

The second counter of 13 pulses, the conversion factor of which is chosen equal to “, provides for unblocking the forbidden state of the device when (at power on or under the influence of impulse noise) the contents of all the memory cells of memory block 8 and register 9 are zero. In this case, during p-2 ^t clocks of the presence of a zero signal at the first output of the 7-flip-flop 2, the second pulse counter 13 will not be reset, and at its output a pulse will be generated that sets the O-flip-flop 12 to one state, which will ensure the restoration of normal

5 modes of operation of the device.

Claims (1)

Claim A pseudo-random number generator containing a clock pulse, the output of which is connected to the input of the 7-flip-flop and the first input of the AND element, the output of which is connected to the first input of the OR-element and the synchronization input of the O-flip-flop, the output of which is connected to the first input 15 of the modulo two whose output is connected to the first information input of the memory block, the address inputs of which are connected to the corresponding outputs of the adder, the first and second groups of inputs of which are connected respectively to the corresponding outputs of the the second pulse counter and with the corresponding outputs of the first group of outputs of the switch, the group of inputs of which is the control inputs of the pseudorandom number generator, the second input of the OR element is connected to the first output of the 7-flip-flop, the second output of which is connected to the second input of the AND element, the output of the OR element is connected to the input control unit of the memory, characterized in that, in order to extend the functionality due to the generation of "-bit non-correlated pseudo-random numbers, a register, a multiplexer and and the second pulse counter, the output of which is connected to the input of the 7) -trigger installation, whose information input is connected to the output of the multiplexer, whose information inputs are connected to the corresponding outputs of the memory block and the corresponding inputs of the register, the ίth output of which is connected to (r + 1) the m information input of the memory block (7 = 1, 2, ..., “-1”), the corresponding register output is connected to the second input of the modulo-two adder and to the installation input of the second pulse counter, the synchronization input of which is connected to the output of the first account A clock whose synchronization input is connected to the register synchronization input and to the first output 7-flip-flop, the output element And is connected to the input of the switch, the second group of outputs of which is connected to the control inputs multiplexer.