SU1305837A1 - Pseudorandom sequence generator - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to increase the reliability of operation and improve the characteristics of the pseudo-randomly generated sequence. To achieve the goal, the element OR 6, the initial installation block 7, the trigger 8, the AND 9 element, the key 10 are entered into the device. The device also contains -; tune device 1, shift register 2, adder 3 modulo two, counter. 4. delay element 5, generator 11 clock pulses, bus 12 Start, bus 13 Installation. Improving the reliability of the device and reducing the correlation of its output pulses is due to the use of a feedback signal from the output of the random access memory 1, 1 sludge. 2 je 11 bxJ (L with bb / L. Co o el oo with -vl g 6 LJ rv -e x /. 3 t / ctnOHO KO 1 Sync. -

Description

The invention relates to a pulse technique.

The aim of the invention is to increase the reliability of operation and improve the characteristics of the generated-pseudo-random sequence.

The drawing shows a functional diagram of a pseudo-random sequence generator;

The pseudo-random post-fo OR 6 and the third (informational contains, operative back) input of the operative storage device пом is the output of which is connected to the input of the sequential shift of the shift register 2, the device 1 is set to the logical level 1, At the same time, the level from the inverse output of the trigger of the corresponding bit of which 15 of 8 translates the shift register 2 is connected to the first input of modulator 3 modulo two, counter 4, delay element 5, element OR 6, block 7 of the initial mouth oks, trigger 8, element 9, key 10, generator 11 clock pulses, bus Start 12, bus Installation 13. Generator output 11 clock pulses are connected to the Synchronization input of the shift register 2 and the counting input of counter 4, output 3 of counter 4, and when it is opened, it is connected to the address key key 10 by the same pulse by the inputs of the operative storage through the time determined by the element of the device 1, the read and write inputs of the delay 5, logical; from the output of which is connected to the output and input element OR 6 is recorded in whose corresponding element 5 is the delay of the operational memory. Bus START 12 is connected to S-device 1, whose address is determined by counter code 4. For recording 1 over the entire required memory array 1, j the time interval between the signal generated by block 7 initial

its third input to the recording mode, clock pulses from the generator output 11 clock pulses are fed to the device and a parallel code pre-installed at its parallel bus inputs is entered into the shift register 2 20 Setting each clock pulse increases by one with the trigger of trigger 8 the direct output of which is connected to the input of the key 10, the output of which is connected to the first input of the element AND 9, the output of which is connected to the input of the element 5. The information input of the random access memory 1 nen yield of OR 6, the first input coupled to the control input of the shift register 2 and the inverted output of the flip-flop 8, R-input coupled to the reset input of the counter 4 and the output unit 7 the initial installation. The output of the operational storage device 1 is connected to the second input of the adder 3 modulo two outputs of which are connected to the second input of the element OR 6i The output of the generator 11 clock pulses connected to the second input of the element AND 9, Bus Setting 13 is connected to the corresponding inputs of the shift register 2,

.The contents of counter 1 with the intergenerator pseudo-random sequence after 55. device in the main mode of operation works as follows; the order can be arbitrary, since

When the power is turned on, the signal from device 1 contains a uniform input of the unit 7 of the initial setup, the formation (All 1).

installation, and the Start-up 1 2 start signal, which takes the device into the pseudo-random 40 sequence generation mode, should not be

less than (N-M) -, where M - capacity

g

counter 4; 7- - the period of the following g

45 clock pulses; N is the total size of the device. In this case, logical 1 is written to the array of random access memory 1 with a volume (N-M). Thus, when

50 when the power is turned on, the initial information is stored in the random access memory 1,

arriving at the second (setup) inputs of the counter 4 and trigger 8, sets the latter to the zero state, which provides an auxiliary mode of operation of the pseudo-random sequence generator.

The single potential from the second (inverse) output of the trigger 8 comes to the first input of the element

The device 1 is set to a logic level 1. At the same time, the level from the inverse output of trigger 8 translates the shift register 2 to the counter 4, and when the key 10 is opened, the same pulse through the time determined by delay element 5 is logical; from the output of the element OR 6 is written into the cell of the operative storage device 1, whose address is determined by the counter code 4. For recording 1 over the entire required array of the operative storage device 1, the time interval between the signal generated by block 7

its third input to the recording mode; Clock pulses from the generator output; 11 clock pulses are input to the device and a parallel code previously set at its parallel bus inputs is inserted into the shift register 2; Each clock pulse is incremented by one unit, and a signal start-up on start-up, start-up 1 2, which translate the device into a pseudo-random sequence formation mode,

less than (N-M) -, where M - capacity

g

4; 7- - the period of the following g

clock pulses; N is the total size of the device. In this case, logical 1 is written to the array of random access memory 1 with a volume (N-M). Thus, when

when power is turned on, initial information is entered into the random access memory 1,

When the key 10 is closed, when the power is turned on in the shift register 2, the obviously non-zero code from the parallel bus inputs is set to 13, However, the zero potential from the first (direct) trigger output 8 clocks on the I element 9, random access memory 1 the second input is constantly in the reading mode, and on the counter 4 a sequential search of codes takes place. Thus, when the key 10 is closed, when the power is turned on, random access information is stored in the RAM 1, but in general, when the power is turned on, the device turns on the information of the type All zeros.

In the drawing, possible links are shown in broken lines that allow one to self-organize the operation of the pseudo-random sequence generator. In this case, the overflow output of counter 4 must be connected to the first S-input of trigger 8, instead of Start 12 bus, and to the synchronization output of the device. In this case, when the power is turned on, the unit 7 of the initial setup emits a pulse and flushes the trigger 8 and the counter 4. The latter successively passes (NM) states and, by a signal of its overflow, the trigger 8 is set to one, the device goes into main mode work. An overflow impulse of counter 4 along the synchronization circuit enters the external circuit and can serve as a start signal for a device using a pseudo-random sequence generator.

Upon arrival of the signal on the bus, Start 12, the trigger 8 is set to a null state and ensures the main mode of operation of the device. The zero potential from the inverse output of the trigger 8 translates the shift register 2 into the shift mode, and the zero and unit potentials from the corresponding outputs of the trigger 8 open the element OR 6 and the element 9 (with the key 10 closed). Clock pulses arrive at the output of AND 9. Each clock pulse increments the contents of counter 4 by one, thereby changing the address of the polled random access memory cell 1. The same pulse reads the selected cell to the first input (serial input) of the shift register 2 and the shift of the number written in shift register 2. At the output of modulator 2 modulo two, a level is formed, determined by the state of the output of the random access memory and the corresponding (last) bit of the shift register 2, connected to its outputs.

After a time ,, determined by the delay element 5, the signal from the output of the adder 3 modulo two is recorded in the interrogated cell of the operative storage device 1. During operation, the counter 4 passes the / (NM) state and a sequence arrives at the serial shift of the shift register 2 binary numbers recorded in random access memory 1 by N times earlier, since the shift register 2 is chosen to be equal to M; As a result, the work performed by random access memory 1 at a given organization uu recording and reading processes, similar to the operation (N-M) discharge register. shift, and the whole circuit of the device can be considered as a common N-bit shift register, the modulo two adder is included in the feedback circuit of which

Using one of the feedback signals from the output of the random access memory 1 in the device improves the reliability of the pseudo-random sequence generator and reduces the correlation of its output pulses.

Claims (1)

Invention Formula A pseudo-random sequence containing a random access memory, the output of which is connected to the serial shift shift input, the output of the corresponding bit of which is connected to the first input of the modulo two, a clock generator, the output of which is connected to the register synchronization input and the counting input of the counter, outputs which are connected to the address inputs of the operational memory devices whose read and write inputs are connected to the output and input of the corresponding delay element, which is so that, in order to increase the reliability of the generator and improve the characteristics of the pseudo-random sequence formed by it, an OR element, an initial setup block, a trigger are entered into it , And element, and the key; bus Start is connected to the S-trigger input, the direct output of which is connected via a key to the first input of the And element, the output of which is connected to the input of the delay element; information input of the operational Editor G, Gerber Compiled by Y. Burmistrov Tehred M. Khodanich Proofreader A. Obruchar Order 1464/54 Edition 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 the storage device is connected to the output of the OR element, the first input of which is connected to the control input of the shift register and the inverse output of the trigger, whose R input is connected to the zeroing input of the counter and the output of the initial installation unit. the output of the operational memory is connected to the second input of the adder two, the output of which is connected to the second input of the OR element, the output of the clock pulse generator is connected to the second input of the And element, the bus The installation is connected to the corresponding inputs of the shift register bits.