SU1247828A2 - Device for correcting time scale - Google Patents

Abstract

The invention relates to radio engineering. In relation to the main author. St. No. 1095431 decreases the correction time with large discrepancies in time scales. The device contains a generator 1, phase shifting; block 2, frequency divider 3, reversible counter 4, shift register 5, six coincidence elements (ES) 6, 13, 14, 15, 16 and 17, assembly element 7, two single pulse generators ( FOI) 8 and 12, correction code converter 9, c4 sensor 10, decoder 11, trigger (t) 18 and control signal generator 19. To correct the time scale, a command is sent to the device input through the assembly element 7. tsD 4 00 y sk go

Description

124

BACKGROUND 12. At the output of the BACKGROUND 12, a pulse is formed, which resets the counter 10. In the code of the decoder 11, the level of the logical unit appears, which is fed to the control input

one

The invention relates to the field of radio engineering and instrumentation and can be used in the construction of synchronizing devices and time keepers of autonomous devices.

The purpose of the invention is to reduce the correction time with large discrepancies in time scales.

FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 and 3 are timing diagrams for the operation of the device; in fig. 4 is a block diagram of the correction code converter; in fig. 5 - time diagrams of the operation of the correction code converter; in fig. 6 is a frequency divider circuit diagram.

The device for correcting the time scale contains a generator 1, a phase-shifting unit 2, a divider 3 hours-TOTbi, a reversible counter 4, a register 5 shift, a coincidence element 6, an assembly element 7, a single pulse shaper 8, a correction code converter 9, counter 10, the decoder 11, the additional shaper 12 single pulses, the first 3, the second 14, the third 15, the fourth 16 and the fifth 17 additional elements of the match, the trigger 18, the driver 19 of the control signals, the correction code converter 9 contains the first 20 and second 21 elements with a trigger, a trigger 22, an assembly element 23, and a delay element 24, and a frequency divider 3 comprises a divider 25, a first 26 and a second 27 assembly elements, a counter 28 of the first time scale, a counter 29 of a second time scale, an inverter 30.

The device for the correction of time scales works as follows.

Corrector 9, allowing the passage of signals through it. The goal is achieved by the introduction of the assembly element 7, BACKGROUND 12, ES 13, 14, 15, 6 and 17 and T 18. 6 Il.

The generator 1 is a source of stable frequency pulses (Fig. 2k) for starting the phase-shifting unit 2, which is designed as a divider.

frequencies with a variable division factor. In the initial state, the division factor of the phase-shifting unit 2 is equal to K, which is determined by the presence at the second control input of the level

logical zero regardless of the voltage of the first control input. From the output of the phase-shifting unit 2, pulses are applied to the input of the frequency divider J3 - the time-keeping.

magicians (Fig. 2l). Frequency divider 3 produces a division of the pulse frequency arriving at its input, to often, for example, 1/60 Hz, the formation of an intermediate grid

frequency, the formation of a double-time code.

To correct the time scale, a command is sent to the device's command input (Fig. 2a). Team through

the assembly element 7 is fed to the input of an additional shaper 12 of single pulses, at the output of which a pulse is formed (Fig. 2b). This pulse resets counter 10

and at the output of the decoder 11 a logical unit level appears (Fig. D) The level of the logical unit from the output of the decoder 11 is fed to the control input of the correction code converter 9 and allows the signals to pass through the first 20 and second 21 elements of the match (Fig. 5c). correction code converter 9.

At the input, the device correction code is supplied with an n-bit sequential pulse binary correction code with high-order bits, and the low-order code contains information about the sign of the correction.

The correction code is given in two lines in the form of a direct and inverse codes, with one in the correction code corresponding to the presence of pulses on the direct code line and the absence of pulses on the inverse code line, and zero corresponds to the absence of a pulse on the direct code line and the presence of a pulse on the line of the inverse code (Fig. 5a and 56).

 These pulses are passed through the first 20 and second 21 match elements to the inputs of the trigger 22 and the assembly element 23 of the correction code converter 9. At the output of the trigger 22, it forms with a direct correction code (Fig. 5e), and the duration of the pulses of the right code is extended to the following period, pulses of the clock series, which is formed at the output of the assembly element 23 (Fig. 5e). Pulses of the clock series from the output of the assembly element 23 through the delay element 24 arrive at the clock output of the correction code converter 9, at the information output of which a direct correction code is formed. Thus, the clock pulses are delayed with respect to the code pulses on the forward and reverse code lines.

From the information output of the converter 9 of the correction code of the discharge of the direct correction code is supplied to the information input of the shift register 5, to the clock input of which delayed clock pulses are sent from the clock output of the correction code converter 9 (Fig. 2d and 5d), and clock delay provides reliable recording of information in the shift register 5.

The forward correction code is written to shift register 5.

At the same time, counter 10 counts the number of clock pulses, i.e. the number of bits of the correction code recorded in shift register 5. As soon as all h bits of the correction code are recorded in shift register 5, the outputs of counter 10 have a double code corresponding to the number of code bits. At the output of the decoder 11, a logic zero level (Fig. 2c) appears, which, entering the control input of the correction code converter 9, prohibits the passage of signals through the first 20 and second 21 coincidence elements (Fig. 5c). This improves the noise immunity of the device.

The level of logical zero from the output of the decoder 11 enters the first input of the driver 8 single im-. pulses. A single pulse shaper 8 selects a second zero-level pulse from a clock series arriving at its second input after its first input, and inverts it (FIG. 2d). This pulse is fed to the second input of the driver 19 of the control signal and to the input of the preliminary recording of the reversible counter 4, and the front of this pulse is used to record information stored in the higher h-1 bits of the shift registers 5 into the reversible counter 4. writing to the reversible counter 4 of a number other than zero, at its output appears the level of the logical unit (Fig. 2e), which, arriving at the first input of the control signal generator 19, enables the formation of a control signal at its output. A control signal in the form of a logic unit level appears at the output of the control signal generator 19 based on the decay of the pulse coming from the generator B of single pulses (Fig. 2g).

The control signal through the first additional element 13 coincidence, opened by the command voltage supplied to the first input, is fed to the second control input of the phase-shifting unit 2 and changes its division factor by Ktl depending on the sign of the correction applied to the first input of the phase-shifting unit 2 from the low-order output of the shift register 5 (FIG. 2). At the same time, the control signal opens the coincidence element 6, allowing the passage of pulses from the output of the phase-shifting unit 2 to the counting input of the reversible counter 4 (Fig. 2i. As in the prototype, one pulse received on the counting input of the reversible counter 4 corresponds to a time scale shift + Tr. In Fig. 2m, as an example, the correction of the time scale with the signs + and - is shown. Fig. 2 l corresponds to the division ratio of the phase-shifting unit 2, equal to.

As soon as the number written in the reversible counter 4 is counted, the logical zero level (Fig. 2e) appears at the output of the reversible counter, which returns the control signal generator I9 to the initial state (Fig. 2g). The logical zero level from the output of the control signal generator 19 locks the coincidence element 6 and the first additional coincidence element 13, and the initial division factor K of the phase-shifting unit 2 is restored.

The correction value ut is equal to

At. where Tg is the pulse following period

at the output of the generator 1; N is the number recorded in the highest n-1 bits of the shift register 5.

To correct the time code, a command is sent to the second command input of the device (Fig. 3a), which, through the assembly element 7, is fed to the input of the additional generator 12 of single pulses. At the output of the latter, a pulse is formed (Fig. 3B), which resets the counter 10. In this case, the output of the decoder 11 shows the level of the logical unit (Fig. 3 Sv). This signal is applied to the control input of the correction code converter 9 and permits the passage of the correction code pulses through the first 20 and second 21 matching elements.

To the input code correction device. The h is given a pulse bit pulse sequential two-code correction code for two lines in the form of a direct and inverse codes. The code has the following structure: the low-order bit is arbitrary, the next m bits are the binary code of the first time scale, the next 1 bits are the binary code of the second time scale, the remaining bits are zero.

The correction code converter 9 generates a forward correction code at the information output and a delayed clock series at the clock output. The correction code is recorded in the shift register 5, while the counter 10 counts the number of clock series pulses (Fig. 3g). As soon as all the rt bits of the code are recorded in the shift register 5, the outputs of the counter 10

according to the Wits binary code, - corresponding to the number h of the bits of the correction code. In this case, a logic zero level appears in the output of the decoder 11 (Fig. 3 Sv), which, entering the control input of the correction code converter 9, prohibits the passage of signals through the first 20 and second 21 match elements.

The logical zero level from the output of the decoder 11 enters the first input of the former B single pulses, which selects the second one after the appearance at the first input of the logical zero level a pulse from the clock series arriving at its second input and inverts it (Fig. RE). This pulse, via the second additional matching element 14, opened by the voltage of the command, is fed to the reset input of the divider 3 frequencies. At the same time, counters 28 and 29 of the first and second time scales of the divider 3 frequency are zeroed. The same impulse comes on. input pre-record reversible counter 4, and on the front of the pulse, the information is copied from shift register 5 to reversing counter 4.

When writing to a reversible counter 4 of a number other than zero, the level of a logical unit (Fig. Ze) appears at its output, which, arriving at the first input of the control signal generator 19, enables the formation of a control signal at its output. A control signal in the form of a logic unit level appears at the output of the control signal generator 19 (Fig. 3g) by the decay of the pulse output from the generator of 8 single pulses with

The same pulse is applied to the R input of trigger 18.

At the direct output of the trigger 18 a logic zero level appears (Fig. GC), and at the inverse output a logic level (FIG. 3L) appears. The control signal from the output of the control signal generator 19 is fed to the second input of the coincidence element 6, allowing passage pulses from the output of the phase-shifting unit 2 to the counting input of the reversible counter 4 (Fig. 3). The information recorded in the reversible counter 4 begins to be read. With this impulses

from the output of element 6 coincidence through the fourth additional element 16 coincidence, opened by the voltage of the command at its first input and the level of the logical unit at its third. the input coming from the inverse output of the trigger 18, is fed to the input of the installation of the first time-divider scale 3 frequency (. Zo). As soon as zeros are written down in the low-order bits of the reversing counter 4, the output level of the third additional element 17 coincides with the level of logical zero (Fig. 3i) and the trigger 11 turns upside down (Fig. 3k and 3l), the fourth additional element The 16 matches are closed, and the third additional match element 15 is opened.

Thus, at the input of the installation of the first time scale of the frequency divider 3, a burst of pulses is formed (Fig. 3m), the number of which corresponds to the binary number recorded in the lower-order bits of the reversing counter 4.

The information recorded in the reversible counter 4 continues to be read. From the output of the f-n-ro discharge of the reversible counter, the pulses go through the third additional coincidence element 15 to the input of the second time-scale divider 3 frequency setting (Fig. 3N). As only all information recorded in the reversible counter 4 is considered, at its output a logical zero level (Fig. Ze) is output. This signal arriving at the first input of the control signal generator 19 returns the latter to the initial state (Fig. ZH). The logic zero level from the output of the control signal generator 19 closes the coincidence element 6 and the supply of pulses to the counting input of the reversible counter 4 stops (Fig. 3k). Thus, at the installation input of the second time scale of the frequency divider 3, a burst of pulses is formed, the number of which corresponds to the binary number written in the higher bits of the reversible counter 4, start with (m + 1) -th bit. The packet of correction pulses of the first scale and the packet of correction pulses of the second scale are fed to the counting inputs of the counters of the first and second scales, respectively.

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Claims (1)

writing them the required time code. Invention Formula A device for correcting the time scale according to ed. St. No. 1095431, characterized in that, in order to reduce the correction time for large discrepancies in time scales, five additional coincidence elements are introduced into it, the assembly element is an additional single-pulse generator and a trigger, the first and second inputs of the assembly element being an input signal. Corrections and a command signal, respectively, while the installation input of the counter is connected to the signal input of the correction input through the serially connected assembly element and the additional single pulse generator c, the output of the driver of control signals is connected to the second control input of the phase-shifting unit through the first additional coincidence element, the second input of which is connected to the first input of the assembly element, the second input of which is connected to the first inputs of the second, third and fourth additional matching elements, The second input of the second additional coincidence element is connected to the output of the single pulse generator, and the code is connected to the input Reset of the frequency divider, the outputs of the third and fourth additional The coincident elements are connected respectively to the installation inputs of the first and second time scales of the frequency divider, the second input of the third additional coincidence element is connected to the output of the tth least significant bit of the reversible counter, and the third input is connected to the forward output of the trigger, the inverse output of which is connected to the second the input of the fourth additional coincidence element, the third input of which is connected to the counting input of the reversible counter. The outputs m of the least significant bits of which are connected to the corresponding inputs of the fifth additional coincidence element, the output of which is connected to the S input of the trigger, the R input of which is connected to the output of the single pulse generator. ldd gp gp r Hh -Sh14 - t  GP g ppppp Пппппппппппппппппппппппппш ;,, J I 2 1-1, gp n ppppppppppppppppppp. t o .J FIG. four Compiled by N. Lebed nska Editor A. Revin. Tehred V. Kadar Proofreader B. Butt ha Order 4123/47 Circulation 398. Subscription VNIIPI USSR State Committee for inventions and discoveries. 113035, Moscow, Zh-35, Raushsk nab. 4/5  Production and printing company, Uzhgorod, st. Project, 4 Schig.6