RU1781669C - Device for correction of time scale - Google Patents

Abstract

The invention relates to the field of radio engineering and can be used in synchronization systems and synchronizing devices. The purpose of the invention is to improve noise immunity. The timeline correction device comprises a generator 1. a phase shifting unit 2. a frequency divider 3, a code converter 4, a shift register 5, a correction code converter 6, a counter 7. a decoder 8. a single pulse shaper 9, a counter 10, a signal distributor 11, an AND element 12, shift register 13, register 14, code comparison blocks 15 and 16, decoder 17, triggers 18 and 19, element And 20. The device provides the ability to receive coded control commands and a repeated correction code. 3 silt

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The invention relates to radio engineering and can be used in synchronization systems and synchronizing devices.

A time scale correction device is known which comprises a generator, a phase shifting unit, a frequency divider, a shift register, a counter, a coincidence element, a reverse counter, a control signal generator, a decoder, a single pulse generator and a correction code converter.

A timeline correction device is also known, comprising a generator, a frequency divider, a time keeper, coincidence elements, two pulse counters, an inverter, electronic keys, two control signal generators and a shift register.

A device for correcting a timeline is also known, which contains a generator, a phase-shifting unit, a frequency divider, electronic switches, two counters, an AND element, an adder, a shift register, a decoder, OR elements, a single pulse shaper, an electronic key block, an inverter, an EXCLUSIVE OR element trigger.

Such devices have low noise immunity, because the influence of noise on the information and control inputs can lead to either a distortion of the correction code recorded in the device, or to the recording of an arbitrary correction code and the start of correction, which means a time scale malfunction.

Closest to the proposed device is a device for correcting the time scale, which is selected as a prototype.

The prototype device comprises a generator, a phase-shifting unit and a frequency divider, as well as a shift register, a correction code converter, a counter, a decoder, a single pulse shaper, an AND element, a trigger, four I elements, an OR element, a pulse shaper, a reversible counter, a control signal shaper , the AND element, the prototype device has an information input for the correction code signal, as well as the control inputs Correction input and Correction,

The prototype device has low noise immunity. This is due to the fact that the influence of noise on the inputs of the input Correction or Correction leads to the operation of the driver, resetting the counter and, as a result, the resolution of the converter of the correction code, the start of the driver and a possible shift of the time scale or failure of the time code.

In addition, the effect of interference on the information input of the device during recording

The correction code can lead to its distortion, and therefore to the correction error, moreover, this error can significantly exceed the error of the time scale storage, which the correction is intended to eliminate.

Thus, the disadvantage of the prototype is its low noise immunity.

The aim of the invention is to increase the noise immunity.

5 The essence of the invention lies in the fact that the device for correcting the time scale, comprising serially connected generator, phase shifting unit and frequency divider, serially connected converter of correction code and shift register, the low-order output of which is connected to the first control input of phase shifting unit, the input of the correction code converter is the information input of the device, the clock output of the correction code converter is connected to the counter input of the counter, the outputs of the bits of the counter through a decoder connected to the first input

0 shaper of single pulses, the second input of which is connected to the output of the phase-shifting unit, the trigger and the first element And connected in series, as well as the second element And, sequentially connected an additional counter, signal distributor and additional trigger, connected in series additional shift register, register, additional decoder and

0 code converter, as well as the first and second code comparison blocks, wherein the information input of the additional shift register is connected to the information output of the correction code converter,

5 the clock output of which through the second element And is connected to the clock input of the additional shift register, the output of the single pulse shaper is connected to the counting input of the additional

0 counter and with the input of the signal distributor, the second output of which is connected to the installation input of the trigger, the third output of the signal distributor is connected to the clock input of the register, and the fourth output

5, the signal distributor is connected to the first control input of the correction code converter and to the second input of the first AND element, the output of which is connected to the start input of the code converter, the first output of which is connected to the second control input of the phase-shifting unit, the output of which is connected to the input of the synchronization signal code converter, the other outputs of which are connected respectively to the reset input and to the installation inputs of the first and second time scales of the frequency divider, the output of which is connected to the second control by the input of the correction code converter and the register setting input, the outputs of the bits of which are connected to the trigger input through the first code comparison unit, the other inputs of which are connected to the outputs of the corresponding bits of the shift register and the first group of inputs of the second code comparison unit, the outputs of the corresponding bits With the exception of the least significant digit, the shift register is connected to the information inputs of the code converter, the control inputs of which are connected to the outputs of the additional decoder, the outputs of the bits of the additional shift register are connected to the second group of inputs of the second code comparison unit, the output of which is connected to the third input of the first AND element, the output of the additional trigger is connected to the second input of the second AND element, the inputs of the counter and the additional counter setting, the third control input of the converter the correction code and the second input of the installation of the additional trigger are interconnected and are the input of the control signal of the device, the output of the control signal of which is the output of the first element I / I

The essence of the invention lies in the fact that an increase in noise immunity is achieved by providing the ability to control binary encoded commands and receive a repeated correction code with a control of the correctness of its reception.

In FIG. 1 shows a structural diagram of the proposed device; in FIG. 2 is a block diagram of the code converter; Fig. 3 is a structural diagram of a correction code converter.

The device for correcting the time scale (Fig. 1) contains a series-connected generator 1, phase shifting unit 2 and a frequency divider 3, as well as a code converter 4, shift register 5, correction code converter b, counter 7, decoder 8, single shaper 9 pulses, counter 10, signal distributor 11, element And 12, shift register 13, register 14, code comparison blocks 15, 16, decoder 17, triggers 18 19, element And 20. The input of the converter 6 is the information input of the device - signal code input correction, and “go informational The th and clock outputs are connected to the corresponding inputs of register 5, the low-order output of which is connected to the first control input of block 2, and the high-level outputs are connected to the information input of converter 4. The first output of converter 4 is connected to the second control input of block 2, and its second, third and fourth outputs are connected respectively to the reset input and to the installation inputs of the first and second time scales of the divider 3. The clock output of the converter 6 is connected to the counting input of the counter 7, the discharge outputs of which through a decoder 8 connected to the first input of the shaper 9. The second input of the shaper 9 is connected to the input of the synchronization signal of the converter 4 and connected to the output of the unit 2. The information input of the register 13 is connected to the information output of the converter 6, the clock output of which through the element And 12 is connected to the clock the input of the register 13, the output of the shaper 9 is connected to the clock input of the distributor 11 and to the counting input of the counter 10, the outputs of the bits of which are connected to the control inputs of the distributor 11. The first output of the distributor the splitter 11 is connected to the first installation input (R-input) of the trigger 19, the output of which is connected to the second input of the element And 12. The second output of the distributor 11 is connected to the synchronization input of the trigger 18, the output of which is connected to the first input of the element And 20. The third output of the distributor 11 connected to the clock input of register 14, the outputs of the bits of which are connected to the first inputs of block 15 and to the inputs of the decoder 17. The outputs of all bits of register 5 are connected to the second inputs of block 15 and to the first inputs of block 16. The output of block 15 is connected to the information trigger input 18. The fourth output of the distributor 11 is connected to the second input of the element And 20 and to the first control input of the converter 6, the second control input of which is connected to the input of the register 14 and the output of the divider 3, The outputs of the bits of the register 13 are connected to information inputs register 14 and to the second inputs of block 16, the output of which is connected to the third input of the element And 20. The outputs of the decoder 17 are connected to the control inputs of the converter 4, the start input of which is connected to the output of the element And 20, Interconnected the third control input of the converter 6, the second installation input (S-input) of the trigger 19 and the installation inputs of the counters 7, 10 are the control

device input - input signal input correction. The output of AND element 20 is the control output of the device,

The code converter 4 (see FIG. 2) contains AND elements 21, 22, 23, a reverse counter 24, a control signal driver 25, an AND-NOT element 26, a trigger 27, an AND element 28, 29. The first input of the AND element 23 is the synchronization input of the converter 4. The output of the And 23 element is connected to the subtraction input of the counter 24, the output of which is connected to the first input of the former 25. The output of the former 25 is connected to the second input of the And 23 element and to the first input of And 21, The second input of And 21 and the first input element And 22 are connected to the control input of the Converter 4, and the formation input of which is the recording entries of the counter 24. The first input of the element And 22 is connected to the first inputs of the elements And 28, 29. The second input of the element And 22, the input of the preliminary recording of the counter 24, the second input of the shaper 25 and the installation input R of the trigger 27 are connected are the start input of the converter 4, The outputs of the lower 5 bits of the counter 24 are connected to the inverse inputs of the AND-NOT 26 element, the output of which is connected to the input of the installation S of the trigger 27. The inverse output of the trigger 27 is connected to the second input of the AND 29 element, the third input to is connected to the output of the element And 23. The output of the nth bit of the counter 24 is connected to the second input of the element And 28, the third input of which is connected to the direct output of the trigger 27. The outputs of the elements And 21, 22, 29 and 28 are respectively the first, the second, third and fourth outputs of the Converter 4.

The correction code converter 6 (see FIG. 3) contains an OR element 30, a trigger 31, AND elements 32, 33, a trigger 34, an OR element 35, and a delay element 36. The first and second inputs of the OR element 30 are respectively the first and second control inputs of the converter 6. The first inputs of the And 32, 33 elements are the information input of the converter 6. The output of the OR element 30 is connected to the input R of the trigger 31, the input S is the third control the input of the converter 6. The output of the trigger 31 is connected to the second inputs of the elements And 32, 33, the outputs of which are connected respectively to the inputs S and R of the trigger 34. The output of the trigger 34 is the information output of the converter 6. The outputs of the elements And 32, 33 through the element LEE 35 connected to the input of delay element 36 whose output is a clock output of the converter 6.

The generator 1 is a stable frequency pulse source for starting the phase-shifting unit 2, which is designed as a frequency divider with a variable division coefficient. In the initial state, the division coefficient of block 2 is equal to K, which is determined by the presence on its second control input of a logical O signal from the first output of converter 4.

The pulses from the output of block 2 are received at the input of the divider 3. The divider 3 divides the frequency of the input signal to 1/60 Hz, forming an intermediate frequency grid, and also counts the time,

minutes and hours. Thus, the divider 3 produces a time scale, which is a set of pulses of the frequency grid (from the frequency of the input signal of the divider 3 to 1/60 Hz) and the time code.

In the proposed device, the correction of the time scale is performed by shifting the scale by changing the division ratio of block 2 (phase correction), as well as

by resetting and then setting the time code (time code correction).

To correct the time scale, a command is issued in the form of a pulse to the control input (input of the signal input correction)

which goes to the inputs R of the counters 7, 10, to the third control input of the converter b and to the input S of the trigger 19. The command is given immediately to the pulse formation field at the output of the divider 3, At the output

a decoder 8, which decrypts the zero state of the counter 7, receives a logical O signal that triggers the shaper 9. At the output of the shaper 9, the second pulse after the start is extracted from the sequence of pulses arriving at its second input of block 2. This pulse is fed to the counter input of the counter 10 and to the clock input of the distributor 11. The counter 10 changes its state by cutting a pulse at the counter input. Prior to this, the zero combination from the outputs of the bits of the counter 10 goes to the control inputs of the distributor 11, which does not pass the signal from the clock input to

one of the exits from the exit. After changing the state of the counter 10 from zero to the state corresponding to unity, the clock input of the distributor 11 is connected to its first output. The logical signal 1 from the output of the trigger 19 is fed to the second input of the element And 12, allowing the passage of signals with. the clock output of the Converter 6 to the clock input of the register 13. In the Converter 6, the pulse from the third control input goes to the input S of the trigger 31

(Fig. 3), the logical signal 1 from the output of which allows the passage of signals through the elements And 32, 33.

A correction code is applied to the device information input (signal input correction code), which has the following structure: the first N bits are the binary command code, the second N bits are the information code. The correction code is transmitted twice. The information code has the following structure: during phase correction, the least significant bit is the sign, the highest bits are the shift of the time scale; when correcting the time code - the least significant bit - the next n least significant bits are the binary code of the minutes, the remaining bits are the binary code of the clock. The serial pulse correction code is transmitted over two communication lines in the form of a code of units and a code of zeros. In this case, the correction code unit corresponds to the presence of a pulse on the unit code communication line and the absence of a pulse on the zero code communication line, and the correction code unit corresponds to the absence of a pulse on the unit code communication line and the presence of a pulse on the zero code communication line .

The pulses of the code of units and the code of zeros are fed to the information input of the converter 6, in which through the elements And 32, 33 they are respectively supplied to the inputs S and R of the trigger 34 and to the inputs of the element OR 35. At the output of the trigger 34, a direct sequential correction code is generated, which arrives to the information output of the converter 6 and then to the information inputs of the registers 5, 13. At the output of the OR element 35, a series of clock pulses is generated, which through the delay element 36 is fed to the clock output of the converters 6 and then to the clock input istra 5, to the count input of the counter 7 and via the AND gate 12 to the clock input of register 13.

The correction code is recorded in registers 5, 13. At the same time, counter 7 counts the number of clock pulses, i.e. the number of written bits of the code. When the first clock pulse arrives at the counter 7’s input, the logic 1 signal appears at the output of the decoder 8, The counter has a conversion factor equal to N, When the first N bits of the correction code (command code) are received, the counter 7 zeroed and at the output of the decoder 8 a logical O signal appears, which starts the driver 9. The pulse from the output of the driver 9 through the distributor 11 (through the third output) is fed to the clock input of the register 14. In this case, the first N bits

The correction code (command code) is transferred from register 13 to register 14. At the same time, the pulse from the output of the shaper 9 enters the counting input of the counter 10, after which the latter changes its state. In this case, the clock input of the distributor 11 is connected to its first output.

The next N bits of the correction code are recorded in the 5.13 registers. At the end of their recording, the counter 7 is reset and the former 9 starts, the pulse from the output of which through the distributor 11 (through its first output) is supplied to the input R of the trigger 19. The logical signal O from the output of the trigger 19 is fed to the second input of the element And 12, allowing passage clock pulses to the clock input of the register 13. In this case, the information part code of the correction code is stored in the register 13, The pulse from the output of the driver 9 is supplied to the counting input of the counter 10, while the clock input of the distributor 11 is connected to its second rum exit.

The device correction code is supplied with a repeated correction code, which completely repeats the originally submitted correction code. The correction code through the converter 6 is recorded in register 5. After the first N bits of the correction code are written in register 5, the counter 7 is reset and the former 9 is started. The pulse from the output of the former 9 through the distributor 11 (via the second output) is fed to the trigger synchronization input 18, into which the output signal of block 15 is recorded at the input D. The binary inputs from the outputs of register 14, i.e. binary command code of the first correction code. The binary inputs of the outputs of the bits of register 5, i.e. binary code of the repeated correction code command. If the command codes match, the output of block 15 generates a logical 1 signal.

The pulse from the output of the driver 9 also enters the counting input of the counter 10, while the clock input of the distributor 11 is connected to its fourth output.

The next N bits of the repeated correction code through the converter 6 are recorded in the register 5, erasing the previously recorded information. At the end of the recording, counter 7 is reset and the driver 9 starts. The pulse from the output of the driver 9 through the distributor 11 (through the fourth output) is supplied to the first control input of the converter 6, in which through the OR element 30 (Fig. 3) it is fed to the trigger input R 31 Signal

logical O from the output of the trigger 31 prohibits the passage of signals through the elements And 32, 33. In this case, it is prohibited to change the state of the outputs of the Converter b.

The pulse from the fourth output of the distributor 11 is also fed to the second input of the And element 20. The third input of the And 20 element receives a signal from the output of the block 16. The first inputs of the block 16 receive the information code of the repeated correction code from the outputs of register 5, and the second inputs receive the code information of the first correction code from the outputs of the bits of the register 13. When they coincide at the output of block 16, a logical 1 signal is generated.

In case of coincidence of the first and repeated correction codes at the first and third inputs of the And 20 element, there are logical 1 signals and the pulse from the fourth output of the distributor 11 passes through the And 20 element to the start input of the converter

4and to the control output of the device, a certificate of correct recording of the correction code and the beginning of the correction.

The binary code of the correction value from the outputs of the highest N-1 bits of the register 5 is received at the information input of the converter. The binary command code from the outputs of the register 14 is decrypted by the decoder 17, the control signals from the output of which are fed to the control inputs of the converter 4.

Converter 4 (Fig. 2) works as follows.

When correcting the phase, from the output of the decoder 17 to the control input of the converter 4, signals are received that provide a logical O signal in the converter 4 at the first input of the And 22 element, and the presence of the logical 1 signal at the second input of the And 21 element, while the elements 22,28 , 29 are blocked and at the second, third and fourth outputs of the converter 4 there is a logical O signal.

At the start input of the converter 4, i.e. the input of the preliminary recording of the counter 24 and the second input of the shaper 25 receives a pulse from the output of the element And 20. At the edge of this pulse, the value of the correction received from the outputs of the highest bits of the register is written to the counter 24

5 through the information input of the converter 4 to the recording entries of the counter 24. At the same time, the output of the last signal is a logical 1, which is fed to the first input of the driver 25, allowing the formation of a control signal at its output. The control signal in the form of logic 1 appears at the output

driver 25 by the cutoff of the pulse at the input of the start of the Converter 4,

The control signal from the output of the driver 25 through the open element And 21 is fed to the first output of the converter 4. At the same time, the control signal allows the passage of pulses from the output of block 2 to the synchronization input of the converter 4, through

0 element AND 23 to the subtraction input of the counter 24. The code recorded in the counter 24 begins to be read. At the end of reading, when counter 24 is reset, a logical O signal appears at its output, which

5 returns shaper 25 to its original state. At the same time, a logic O signal appears at the first output of converter 4 and the passage of pulses through the AND element 23 is prohibited.

0 Thus, a pulse is generated at the first output of converter 4, the duration of which is proportional to the amount of correction.

The pulse from the first output of converter 4 is fed to the second control input of block 2, changing its division coefficient by K ± 1 depending on the correction sign received at the first control input of block 2 from the output of the low-order bit of register 5. This leads to the shift of the time scale formed by block 3, by

At ± MT; where M is the correction value;

5 T is the pulse repetition period of the generator 1.

When correcting the time code from the output of the decoder 17 in accordance with the given command contained in the correction code,

0 to the control input of the transducer 4 receives signals that provide in the transducer 4 at the first input of the And 22 element a logical 1 signal, and at the second input of the And 21 element - a logical O signal.

5, a logic O signal is supported at the first output of converter 4.

Similarly to the previously considered case of phase correction, the pulse from the output of the And 20 element starts the converter 4, at which the correction value is written to the counter 24, the control signal 25 is generated at the output of the block 25, and the code recorded in the counter 24 is read.

5 (Fig. 2), the pulse from the start input through the open element And 22 is fed to the second output of the converter 4. At the same time, the pulse from the start input sets the trigger 27 to zero, the logical O signal from its direct output prevents the signals from passing through the And 28 element , and the logical 1 signal from the inverse output allows the passage of signals through the And 29 element.

As already indicated above, the code of the correction value in the case under consideration has the following structure: the lower n bits are the binary code of the minutes, the high bits are the binary code of the clock.

As you read the code recorded in the counter 24, the pulses from the output of the element And 23 through the element And 29 are fed to the third output of the converter 4. The outputs of the lower p bits of the counter 24 are connected to the inverse inputs of the element AND-NOT 26. When zeroing the lower bits of the counter 24, i.e. when the minute code of the correction amount is read, the output of the AND-NOT 26 element is a logical O signal, which sets the trigger 27 to a single state. In this case, the logical O signal from its inverse output prohibits the passage of signals through the And 29 element, and the logical 1 signal from the direct output allows the signals to pass through the I / I 28 element.

The code recorded in counter 24 continues to be read. In this case, pulses from the output of the nth bit of the counter 24 through the And 28 element are fed to the fourth input of the converter 4.

At the end of the code reading, when the counter 24 is reset, a logical P signal appears at its output, which returns the former 25 to its initial state. In this case, the passage of pulses to the input of the subtraction of the counter 24 is prohibited.

Thus, when the time code is corrected, a pulse is generated at the second output of the converter 4, and then first at the third, and then at the fourth outputs of the converter 4, pulse packets are formed, respectively, of minutes and hours in accordance with the correction amount.

The pulse from the second output of converter 4, as well as the bursts of pulses of minutes and hours from its third and fourth outputs, respectively, are fed to the reset input and to the installation inputs of the first and second time scales of the divider 3, while the time code is first reset {reset the minutes and hours counters ), and then setting up a new code (filling in the minute and hour counters with corresponding bursts of pulses).

The next pulse from the output of the divider 3 is fed to the input of the register 14 and nullifies it. At the same time, the outputs of the decoder 17 also display logical O1 signals blocking the operation of the converter 4. At the same time, the pulse

from the output of the divider 3, it enters the second control input of the converter 6, in which (see Fig. 3), through the OR element 30, it enters the input K of the trigger 31. 5 is confirmed to be its zero state.

In case of mismatch of any of the parts (command code or information code) of the first and repeated correction codes at the output of trigger 18 or (and) at the output of block 16, there is a logical O signal that prevents the pulse from passing through element 14 20 to the start input of converter 4 , At the same time, there is no signal at the control output of the device, which indicates an error in writing the correction code and the impossibility of the correction, it needs to be repeated.

 In the event that after applying a pulse to the input, the input of the device correction code

For any reason, correction cannot be applied or is not completely supplied; restoration of the initial state of converter 6 is performed by a pulse from the output of divider 3, on which pulses with a frequency of 1/60 Hz are generated 5 s. This pulse is fed to the second control input of the converter 6, in which through the element OR 30 (Fig. 3) the trigger 21 is reset. This imposes restrictions on the interval

0 of the time for the correction of the time scale, which must be completed before the pulse is formed at 1/60 Hz at the output of the divider 3.

Claims (1)

The claims 5 A device for correcting a timeline comprising serially connected generator, phase shifting unit and frequency divider, serially connected converter of correction code and Q shift register, the low-order output of which is connected to the first control input of the phase-shifting unit, the clock output of the correction code converter is connected to the counting input of the counter, BYPASS 5 bits of which through decoders are connected to the first input of the single pulse generator, the second input of which is connected to the output of the phase-shifting unit, the trigger and 0 are connected in series to the first element And, as well as the second element And, and the input of the correction code converter is the information input of the device, characterized in that, in order to increase the noise immunity, in 5, an additional counter, a signal distributor and an additional trigger are connected in series, additional shift register, a register, an additional decoder and a converter are connected in series code, as well as the first and second blocks of code comparison, while the information input of the additional shift register is connected to the information output of the correction code converter, the clock output of which through the second element And is connected to the clock input of the additional shift register, the output of the single pulse generator is connected to the counting input of the additional the counter and with the input of the signal distributor, the second output of the additional counter and with the input of the signal distributor, the second output of which is connected to the installation trigger input, the third output of the signal distributor is connected to the clock input of the register, and the fourth output of the signal distributor is connected to the first control input of the correction code converter and to the second input of the first AND element, the output of which is connected to the start input of the code converter, the first output of which is connected to the second the control input of the phase-shifting unit, the output of which is connected to the input of the synchronization signal of the code converter, the other outputs of which are connected to the reset input and to the installation inputs howling and the second timeline frequency divider whose output is connected with the second control input of the correction code converter and with the register setting input, the bit outputs of which are connected to the trigger input through the first block comparing codes, the other inputs of which are connected to the outputs of the corresponding bits of the shift register and with the first group of inputs of the second block of code comparisons, the outputs of the corresponding bits of the shift register with the exception of the least significant bit are connected to the information inputs of the code converter, the control inputs of which are connected to the outputs additional decoder outputs the bits of the additional shift register are connected to the second group of inputs of the second code comparison unit, the output of which is connected to the third input of the first element And, and the output of the additional trigger is connected to the second input of the second element And, the inputs of the counter and additional counter setting, the third control input of the converter correction code and the second input to install additional the flip-flops are interconnected and are the input of the control signal of the device, the output of the control signal of which is the output of the first AND element,