SU1265755A1 - Information input-output device - Google Patents

Description

1 The invention relates to computerized automation and can be used in devices with input from the keyboard. The purpose of the invention is to increase the speed of the device. FIG. 1 shows a block diagram of the device; in fig. 2 is a functional circuit of the control unit; FIG. 3 is a time diagram of the device. The device (Fig. 1) contains a keypad 1, operation keys 2, encoder 3, first decoder 4, control unit 5, synchronization unit 6, first 7 and second 8 registers, multiplexer 9, display unit 10, second digit keys 11, 12, the first 13 and third 14 counters are registers, the third decoder 15, trigger 16, the fourth counter register 17, the second decoder 18, the pulse generator 19, the second 20, the first 21, the fourth 22 and the third 23 elements I. The control unit 5 (FIG. 2) contains the trigger 24 operations Level, the trigger 25 of the Set mode, the shaper 26 of the zero pulse, ne The first inverter 27, the first AND-OR-HE element 28, the second inverter 29, the first AND-NOT element 30, the delay unit 31, the first driver of the 32 pulses, the second AND-OR-NE element 33, the integrator 34, the Correction trigger, 35 trigger selection trigger 36, coincidence circuit 37, second 38 and third 39 AND-NOT elements, second pulse shaper 40, fourth AND-HE element 41 third 42 and fourth 43 pulse shapers. The device operates as follows. In the initial state, the synchronization unit 6 (FIG. 1) generates signals arriving at the address group of inputs A, A of information registers 7 and 8, at the address group of inputs of multiplexer 9 and at the address group of inputs A, - AJ, block 10 of the display, indicating the data arriving at its information input and at the data input of registers 7 and 8 from the output of the multiplexer 9, whose information inputs receive signals from the information Q outputs of the counters-register 12-14, in zero state. Depending on the nature of work with the device for entering and outputting information, the operator presses a key on the keyboard 1. These operations can be Level, Setting a new value, Selecting a corrected bit, Correction of the selected bit up, Correction of the selected bit down. Suppose that the operator sets the output level of the generator. To do this, the operator presses the Level-Password key to access the generator in order to set or adjust the value of the output generator level. In this case, the encoder 3 converts the decimal operation code into a binary four-digit code formed at the first output of the encoder 3 and arriving at the first inputs of the decoder 15 and 4. At the second output of the encoder 3, a pulse is generated (Fig. 3, a). operations that arrive at the first input of the trigger 16 and to the second input of the decoder 15. When the code matches the first output of the encoder 3 of the start combination, the impulse tracking level of this code from the output of the decoder 15 receives a pulse (Fig. 3.6) on the second This is the trigger input 16. When the pulses coincide at the first and second inputs of the trigger 16, the potential (fig, 3i &) of the operation of the decoder 4 is received at its output, entering 1st at its second input. In this case, the binary four-digit binary code is deciphered by the impulse (Fig. 3.0 |) of the operation code received at the third input of the decoder 4, and the signal (Fig. 3.2) from the output of the decoder h is fed to the input set to 1 trigger 24 of the control unit 5, setting the trigger 24 of the operation Level (FIG. -2) to state 1 (FIG. 3, a). Next, the operator presses the operation key Set new value. In this case, the encoder 3 converts the decimal operation code into a binary four-digit code, which is decoded by the decoder 4. From its output signal (FIG. 3, e) is fed to the installation input to 1 trigger 25 of control unit 5, the trigger 25 Set to state 1 (Fig, 3, g).

312657554

The signals of logical 1 from the outputs to the output of the second element I-SHI-HFJ

trigger 24 of operation. Level I33: a pulse is formed (Fig. 3, m),

the trigger 25 of the Set mode comes in through the third output of the block

To the first and second inputs of the formate-5 control to the second input, the decipher 26 zero pulse of the corresponding 5 is 18. Since in the Set mode

venno. The signal received at the input of the third input of the decoder 18, its

installation in 1 trigger 25 and block the fourth and fifth inputs installed

5 control, enters the third signal of logical O (fng.Z, o, p, p,.)

the input of the imaging device 26 pulse zero-respectively from the fifth, seventh

In the presence of the first and second and eighth outputs of block 5 of the control inputs of which signals 1, an impulse appears at its output (Fig. Fp) arriving at the first output of control unit 5. This signal goes to the inputs of the installation in O of registers 12, 13, 14 and 17, he folded them. After that, the operator sets the level of the output signal of the generator, successively pressing the keys of the 11 digits (the digit of the highest decimal digit is dialed first). At the same time, the encoder 3 converts the decimal digit code into the binary code generated on er About the first output, which goes simultaneously to the information inputs of the register counters 12, 13, 14 and 17. The third output of the encoder 3 generates a pulse (Fig. 3, i) tracking the digit code that goes to the second input of the control unit 5. It enters through an inverter 27 to the first inputs of an AND-OR-HE element 28, to the second input of which a signal is applied

logical G from the output of the trigger 25 35inverter 27 to the first inputs of the element of the Set mode. From the output of the first AND OR NOT 28. From its output through the IN-element AND-OR-NOT 28 impulse through the inverter 29 this impulse c arrives at the second inverter 29 enters the first-first input of the element AND-NOT 30, with the input input of the AND-NOT element 30, on the second inlet of which this impulse (FIG. 3K), whose input is received by the logic signal, is supplied to the input of the increase of 1 at 1 from the output of the Trigger 25 of the Dialing mode. From the output of the first element AND-NOT 30 (Fig. 3, k) the pulse arrives at the second output of the control unit 5, the arrival at the magnification input of 45 decoder 18 forms a pulse unit of the counter state 17, re- (Fig. 3, c), arriving at the third water is in state 1, from the information input of control unit 5, the incoming outputs of which this code is the first input of the installation in the trigger O is fed to the first inputs of the decoded-25 dialing mode. At its output is 18. An impulse from the output of the first element 50 Forms the signal (Fig. Zl) of the logic AND-OR-NOT 28 through an O, which prohibits the delay unit 31 from passing to the first driver 32 pulses. From its output, a pulse (Fig. 3, L) is fed to the first inputs of the second element AND-OR-NOT 55 33, to the second input of which through the integrator 34 a signal arrives (Fig.) From the output of the trigger 25 of the Set mode.

To fit the contents of the counter-register 17, set at its output the code number of the counter-register 14.  At the same time, at the fourth output neither, by a pulse at the third output of control unit 5, the formation of a pulse is generated at the first output of the first group of outputs of the decoder 18.  A signal of logical G is set on its second and third groups of outputs.  This pulse arrives at the input of the counter-register record 12. Thus, the first dialed digit is written into the counter-register 12.  When the next digits are dialed, the connection of the bit selection counter 17 is increased by one.  This leads to the appearance of recording pulses successively at the remaining outputs of the first group of outputs of the decoder 18, which arrive at the recording inputs of the remaining counters-registers. 13 and 14.  When dialing the last significant digit to be recorded in the counter register 14 of the youngest bit, the impulse to maintain the binary code of this digit comes from the third code of the encoder 3 via inverted pulses of the code of the numbers from the third output of the encoder 3 through the AND-OR-NOT element However, the logical O signal at the output of the integrator 34 (FIG.  3, m) is set at a time exceeding the time of passage of the pulse (Fig. 3, l) From the output of the driver of 32 pulses through the second element AND-OR-HE 33 (FIG.  ), when writing the last significant digit in the counter-register 14.  After that, when the operator dials any more digits, they are not recorded in the device.  The information recorded in the counters registers 13, 12 and 14, comes from their outputs Q to the information inputs B, B.  , VC, multiplexer 9, which converts a parallel code into a serial one, coming to the data input of the display unit 10, constructed according to the principle of dynamic digital display.  .   Thus, the operator can control the input of each digit of the set value of the output voltage level.  When the operator presses the Enter key, its decimal code is converted by the encoder 3 into a binary four-digit code formed on the first output of the encoder 3.  At the second output of the encoder 3, a tracking pulse is generated for this function code, according to which the binary four-digit code from the first output of the encoder 3 is converted by the decoder 4 to a signal (Fig.  3, d) entering the input. installation in About trigger.  24 of the control unit 5, setting the trigger of the operation 24 Level to the initial state O (FIG.  3, a) and simultaneously arriving at the fourth output of the control unit 5, the arrival at the first input of the imaging unit 19 of the pulse train.  Shaper on output.  19 bursts of pulses pulses are formed (fig.  3, and), arriving at the so-called inputs of registers 7 and 8.  The number of pulses in a burst is equal to or greater than the number of registers 7 and 8, and the period in which these pulses are determined is the clock frequency of synchronization unit 6 and is equal to the polling period of the counter registers 12-14 by the multiplier, Since the address inputs of registers 7 and 8 and multiplexer 9 arrive the same. the address code from the group of outputs of the synchronization information block 6 & the outputs of the register-registers 12-14 are rewritten into the corresponding registers 7 and 8.  Thus, as the new output level value is recalled, the information is indicated by the display unit 10, but the output signal level does not change.  After a set value of the voltage level of the output signal is obtained, the information is output from the device: overwriting the information from the counters-registers 12-14 into registers 7 and 8, the outputs of which are the output of the device.  At this point, the input-output of the smooth output voltage is terminated.  The time required for input-output of information at eight digits in the value of the set level of the output signal voltage is 11 times longer than the time for pressing one key.  If it is necessary to change the previously entered value of the output signal of the generator, the operator can make a change in the dialed number before outputting information from the device, for example, in case of an error when outputting information, or change the dialed number after entering information, for example, when I / O are several output level values generator.  To change the dialed number before displaying information from the device, for example, in the event of an input error, the operator after typing the numeric value of the generator output signal does not press the Enter key, but presses the Select correctable bit key.  In this case, the encoder 3 converts the decimal operation code into a binary four-bit code, which is decoded by the decoder 4.  WITH. its output signal (FIG. 3, p) is fed to the input of the installation in 1 of the trigger 35 of the control unit 5, setting the trigger 35 of the Corr-mode.  state to logical 1 (FIG.  , x) and at the same time trigger. , 36, the choice of bit is also in the state of logical 1 (FIG. H. and).  The signal O from the inverse output of the trigger 35 of the Correction mode is fed to the second input of the installation in O of the trigger 25 of the Set mode, resetting it to its initial state (Fig.  3,) to), install. at its output signal O.  After that, the operator presses the key of the digit with the number of the dialed digit, which it has previously set so in order.  For example, to correct the second dialed digit in order, you must press the number 2 key. In this case, the decimal digit code is converted by the encoder 3 into a binary code received from its first output at the information inputs of the counters-registers 12, 13, 14 and 17 and the fourth input of the control unit 5, at the input of the coincidence circuit 37, the keys with an enabled bit code - the bit code that can be corrected, at the output of the matching circuit 37, there is a logic level 1 which arrives at the first input of the second AND-NE element 38 and the second input has a logic 1 from the direct output of the trigger 36 razr Yes.  From the inverse of the last output, the logical O signal is fed to the first input of the third element IS-NOT 39, the second input of which contains the logical 1 signal from the output of the trigger 24 of the Level operation.  At the output of the third element IS-HE 39 there is a logic level 1 (FIG.  3, o), which comes to the fifth output of the control unit 5, arriving at the third input of the decoder 18, prohibits its operation.  Impulse (FIG. H. v) tracking the digit code from the third output of the encoder 3 Enters the second input of the control unit 5, coming through the first inverter 27 to the first inputs of the first AND-OR-NOT 28 element.  Since the third input of the first element AND-OR-NO 28 receives a logical 1 signal (FIG. Zd) from the direct output of the Trigger mode of the Correction mode, at the output of the first AND-OR-NOT 28 element, a pulse is received through the second inverter 29 to the third input of the second element AND-NOT 38, a logical signal is set at the first and second inputs of which t.  This causes the appearance of a logical O signal at the output of the second element IS-NOT 38, which triggers the second pulse shaper 40.  A pulse is formed at the first output of the latter (FIG. H. h)  It prohibits the passage of a pulse (FIG.  3, /) through the second AND-OR-HE element 33 To the third output of the control unit 5 from the output of the first shaper 32 pulses, triggered through the delay block 31 by the signal from the output of the first AND-OR-HE element 28, and zeroing the bit trigger 36 Yes.  Thus, the pulse at the output of the second element AND-OR-HE 33 does not appear (Fig. H. n) and the work enable signal is not provided to the second input of the decoder 18.  At the same time, a pulse comes from the second output of the second pulse shaper 40 (FIG. H. Io of resolution for nepijfjrii input of the fourth element IS-NOT 41, to the second input of which a signal of logical 1 is received (Fig. 3 | X) from the output of the trigger 35 of the Correction mode, and to the third input - an impulse (FIG. H. and) from the output of the first imager 32 pulses.  As a result, a pulse is generated at the output of the fourth AND-HE element 41 (FIG. 21 c) arriving at the sixth output of the control unit 5, which arrives at the TOBtim input of the parallel recording of the counter-register 17, writing to it the binary code of the digit from the first output of the encoder 3.  From the information Q-codes of the counter-register 17, the binary-code of the selected correction bit is fed to the group of first inputs of the decoder 18.  This completes the selection of the adjusted bit.  Thus, in contrast to the known device, the choice of a corrected bit is made during two keystrokes, which significantly reduces the correction time in several bits of a set number.  For eight significant digits of a number during correction, for example, in the second and eighth digits of a number, a time equal to eight keystrokes is required to select the correctable bits in the known device, which is equal to the time of the new dialing number.  In the device, a time equal to four keystrokes is required to select the corrected second and eighth digit bits.  If it is necessary to increase the content of the selected corrected bit, the operator will have the Correction key of the selected bit up. In this case, the decimal key code of this operation is converted by the encoder 3 into a binary code.  From the first output of the encoder 3, the binary operation code arrives on; The first entry is a decoder 4.  When a pulse arrives at its third input (FIG.  3, a) tracking the operation code from the second output of the encoder 3 at the output of the decoder 4, a pulse arrives at the input of the third pulse generator 42 of the control unit 5.  With the release of the third form. The bodies of 42 pulses A short pulse arrives at the fifth input of the second element AND-OR-HE 33.  Since at the fourth inputs of the second I-SHSh-33 element there is a logical 1 signal from the direct Trigger 35 of the Correction mode, a short pulse is generated at the output of the second AND-OR-33 element (Fig. H. n), arriving at the third output of the control unit 5, arriving at the second input of the decoder 18, allowing its operation for the duration of this pulse.  From the input of the generator 42 of the control block 5, the signal (FIG.  3, p) enters its seventh output, arriving at the fourth input of the decoder 18, which leads to the switching of the outputs of the latter.  When a pulse pulse arrives at its second input, a pulse is formed at the corresponding output of the second group of the decoder 18, the input of an increase in the unit of the counter-register state COOT corresponds to the counter-register 17 state (or through element 20, 21 if any bit except the first).  The maximum possible state of the counter-register 17 corresponds to the selection of the least significant bit of the counter-register 14.  The unit state of the counter-register 17 corresponds to the selection of the most significant bit of the counter-register 12 - the first significant digit to be dialed.  If, when correcting in the direction of increasing the number in the bit, for example at the lowest bit of the counter-register 14, the gap completes this bit, then at the output of the P9 counter of the register-register 14 there appears a pulse arriving at the first input And 20, the output of which this pulse arrives at the input of the increase per unit state of the counter-register 13 - as a higher order bit, and in the counter-reg. line 14 is set to zero. that notion.  When correcting in the direction of increasing the discharge on the counter-register 13, a pulse from the output of the second group of output of the decoder 18 is fed to the second input of the element AND 20, from the output of which the pulse arrives at the input of the increase per unit of the counter-register 13, and its state increases on a unit.  The state of the remaining reversible register counters does not change.  From the seventh output of the control unit 5, the signal arrives at the second input of the pulse generator 19 of the pulse train, starting it (Fig. H. y), as a result of this, the corrected number goes to the output of the device, the multiplexer 9 and the corresponding register 7 or 8 pass.  .  . The time required for input is equal to the time of pressing a single key. If necessary, monotonously reduce the contents of the selected bit, the operator presses the Correction key of the selected bit down.  In this case, the decimal key code of this operation is converted by the encoder 3 into a binary code.  From the first output of the encoder 3, the binary operation code arrives at the first input of the decoder 4.  When a pulse arrives at its third input (FIG.  3, a) tracking the operation code from the second output of the encoder 3 at the output of the decoder 4 a pulse is input to the input of the fourth pulse generator 43, from the output of which a short pulse arrives at the sixth input of the second element AND-OR-HE 33.  Since at the fourth inputs of the second element AND-OR-HE 33 there is a logical 1 signal from the direct output of the Trigger trigger 35 of the Correction mode, a short pulse is generated at the output of the second AND-OR-HE element 33 (Fig.  3 | H), arriving at the third output of control unit 5, arriving at the second input of the decoder 18, allowing its operation.  From the input of the control signal block 5 (FIG. 3, p) arrives at its eighth exit, the arrival at the n - th entrance of the decoder 18, which leads to a crossing of the outputs of the decoder 18.  When a short pulse arrives at its second input (FIG.  3, n) an impulse is formed at the corresponding output of the third group of the decoder 18, arriving at the decrease input by one state of the counter-register corresponding to the state of the counter-register 17 of the choice of the discharge (or through element 22, 23 if any bit is corrected except the first).  If, when decreasing the number in the bit, for example, at the lowest bit of the counter register -14, the number decreases to less than zero, then the output of the reversible counter of the register 14 appears a pulse arriving at the first input of the AND element 22, from the output of which this pulse enters the decrement input of the state of the counter-register 13 — as a Higher-order bit, and in the counter of the register 14 is set to state 1 and nine.  When correcting in the direction of decreasing the discharge on the counter-register 13, a pulse from the output of a group of third outputs of the decoder 18 is fed to the second input of the element 22, from the output of which a pulse is fed to the reduction input per unit of the counter-register 13, and its state decreases by one The state of the remaining counters-registers does not change.  From the eighth output of the control unit 5, the signal arrives at the third input of the imaging unit 19 of the burst, triggering it {FIG. 3 | 1 (), as a result of which the corrected number goes to the output of the device, having passed multiplexer 9 and the corresponding register 7 or 8.  If there is no need for a monotonous increase or decrease in the state of the selected bit, the operator can immediately write the required value to this bit.  To do this, the operator, after selecting the corrected bit by pressing the Select correct bit key and the digit key corresponding to the corrected bit in the order of information input, presses the key of the digit that should be set in the selected corrected bit.  At the same time, the tenth key code of the digit, which the operator writes to the adjustable bit, is converted into binary code by the encoder 3. From its first output, this code goes to.  information inputs of register counters 12-14 and 17.  Impulse (FIG.  3, and) tracking the binary code of the digit from the third output of the encoder 3 is fed to the second input of the control unit 5, passing through the first inverter 27 to the first inputs of the first AND-OR-28 element.  Since the signal of the logical 1 is set at the third input of this element (FIG. H. x) from the direct output of the Trigger mode of the Correction mode, at the output of the first element AND-OR-HE 28 a pulse is generated; through the delay unit 31, the first driver 32 starts the pulse-; ow, from the output of which the pulse DD) enters the first inputs of the second element AND-OR-NOT 33.  Since the third and fourth of its codes are signals of logical 1 (FIG. 3,4) from the first output of the second pulse shaper 40 and logical 1 (FIG. H. g) from the output of the trigger 35 of the Correction mode, respectively, then at the output of the second element AND-OR-HE 33 a pulse is formed (Fig. 3, n), arriving at the third output of the control unit 5.  the arrival of the second input of the decoder 18.  Hack as on his third, fourth. and the fifth inputs are set to the logical signals O from the fifth, seventh and eighth outputs of control unit 5, respectively, then the output from the group of first outputs of decoder 18 is a pulse arriving at the clock input of the parallel recording of the counter-register corresponding to the code written in counter-register y.  g this adjustable bit is written to the binary code of the digit key that the operator pressed.  When the operator presses the other keys of the digits, the binary code of these digits is written into the same counter-register.  Simultaneously, the digit code tracking impulse comes from the output of the first inverter 27 to the first input of the fifth IS-NOT element 44, the second input of which has a logical 1 signal from the direct output of the Correction mode trigger 35.  This causes the output of the fifth element AND-NOT 44 pulse arriving at the ninth output of the control unit 5, which arrives at a quarter: the input of the imaging unit 19 bursts of pulses.  Pulses appear at its output (Fig. H. y , rewriting information from reversible register counters through multiplexer 9 into corresponding registers 7 and 8, the outputs of which are the outputs of the device.  I.  Thus, the corrected information is instantly output from the device.  In contrast to the known device, the correction of information occurs in the selected bit during a single press of a key, without having to press a key several times to increase the bit. Correction of the selected different

p or up or Correction of the selected bit, which is what the device’s speed is.

In the known device, to change the number 2 to the number 7, it is necessary to press the keys five times either Correction of the selected bit upward or Correction of the selected bit downward, in the proposed device just one keystroke.

If necessary, type a new one. the number or return the device to the initial state, the operator presses the Enter operation key, and the decimal code of this key is converted by the encoder 3 into the binary code received from its first output to the first input of the decoder 4; From the second output of the encoder 3 a pulse (fig.Z.ch) accompanied by a binary operation code goes to the third input of the decoder 4, which receives a pulse from the output (fig.Zd) to the input of control block 5, transfer trigger 24 operations Level and trigger 35 of the Correction to zero state. Thus, the device is reset. The known device has sufficient complexity due to the fact that with automatic control, in order to select a corrected bit, it is necessary to form a packet of correction pulses. Moreover, the number of pulses in a burst is determined by which digit of the number will be corrected and which digit of the number will be corrected before. The difference between the digits of the bits and determines the number of correction pulses in the pack. In addition, it is necessary to know which command to send to control the device: Selecting the corrected right-to-left bit or Selecting the correctable bit from left to right, as well as what bit of the number has been corrected before, otherwise the input time will be too long, which reduces the speed in device control and device speed. In case of remote control, for example, from the remote keyboard, the operator needs to control such information on the display unit.

Claims (1)

automatic control, since the choice of the corrected bit is made without taking into account which number of the number has been corrected before. Moreover, at any given time it was determined which commands should be given to select a corrected bit. The choice of a corrected bit is made during two key presses, regardless of the number of adjustable bits of the parameter to be set. This makes operational management easier to manage, especially with a device and increases the speed of the device. In the known device, it is possible to select a corrected value in which information is not recorded. Thus, when setting the value of 10 kNg on the display unit, with six significant digits, the frequency of the generator according to Table 2 can be set. 1. Table 1 Choosing a corrected bit, you can randomly choose an insignificant bit of a number, i.e. third and higher. When correcting the value of bits in the direction of decreasing, for example, the fourth bit on the display of the display unit, the number 999010 kNg is set, which makes control of the device incorrect, and in case of an error in the choice of a corrected bit, the number input is incorrect, which reduces the accuracy of information input. In the proposed device, when dialing 10 kNg on the display unit of the device, if you select any correctable bit, a significant bit of any number will be selected. Control the device correctly when selecting any adjustable bit. This increases the reliability of the input information and prevents incorrect control of the device. The device for input and output of information, comprising an encoder, two decoder, three counter-registers, two registers, a multiplexer, a display unit, a synchronization unit, a control unit and a keyboard, the outputs of which are connected to the first inputs of the encoder, the first output of which is connected to the first input the first decoder, the output of which is connected to the first input of the control unit, the second input of which is connected to the third output of the encoder, the second output of which is connected to the third input of the first decoder, the outputs of the groups Synchronization unit s are connected to information inputs of a group of first and second registers, whose outputs are device outputs, synchronization unit group outputs are connected to multiplexer address inputs, and to information inputs of a display unit group whose information input is combined with information inputs of the first and second registers and connected to the output of the multiplexer, the information inputs of which are connected to the information outputs of the first to third counters-registers, whose information inputs connected to the output of the encoder, which is so that, in order to increase the speed of the device, a third decoder, a trigger, a fourth counter-register, a pulse builder, four I elements, the first input of the third decoder is connected to the first output of the encoder, and the second input is combined with the first input of the installation in About the trigger and connected to the second output of the encoder, the output of the third decoder is connected to the second input of the installation in About the trigger, the output of which is connected to the second input of the first decoder, info The fourth input of the counter-register is connected to the first output of the encoder, and the output is connected to the first input of the second decoder, the first output of the control unit is connected to the installation inputs of the first to fourth counters, the summing input of the fourth counter-register is connected to the second output control unit, the third output of which is connected to the second input of the second decoder, and the fourth output - to the first input of the pulse generator, the fifth output of the control unit is connected to the third input of the second an encoder whose group outputs are connected to the gate inputs of the first to third register counters, the third input of the control unit is connected to the first output of the second decoder, the fourth input of the control unit is under-. the keys to the first output of the Ashfrator, the sixth output of the control unit is connected to the gate input of the fourth counter register, the fourth input of the second decoder is connected to the second input of the pulse generator and is connected to the seventh output of the control unit, the eighth output of which is connected to the fifth input of the second decoder and to the third input of the pulse generator, the fourth input of which is connected to the ninth output of the control unit, the overflow output of the first counter-register is connected to the first input of the first I element, the output of which is connected to the summing input of the second counter register, and the second input of the first element I connected to the second output of the second decoder, overflow output of the third counter register and connected to the first input of the second element I, whose output is connected to the summing input the first counter of the register, and the second input of the second element I is connected to the third output of the second decoder, the output of the loan of the first counter register is connected to the first input of the third element I, the output of which is connected to the input of the Tany second counter-register, and the second input of the third element. And connected to the fourth output of the second decoder, the output of the loan of the third counter-register is connected to the first input of the fourth element, And the output is connected to the subtractive input. the first counter-register, the second move of the fourth element I is connected to the fifth output of the second decoder. the sixth and seventh outputs of which are connected to the summing and subtracting inputs of the third counter-register, respectively, the output of the block to the input of the pulse builder, the output of which is connected to the synchronous inputs of the first and second registers. : sync is connected to p