SU1495775A1 - Device for data input - Google Patents

Abstract

The invention relates to automation and computing and can be used to manually enter information into control and computing systems. The purpose of the invention is to increase the speed of the device due to the rapid correction of information. Introduction of the Output, Reverse and Step control keys to the keyboard and the inclusion in the design of the display unit, counter, display element, three triggers, three AND elements and two OR elements made it possible to organize the editing mode of the typed information. When an error is detected, the operator selects the desired bit using the "Reverse" and "Step" keys and corrects the information. To send the typed message, press the "Output" key. 2 Il.

Description

The invention relates to automation and computing and can be used to manually enter information into control and computing systems.

The purpose of the invention is to increase the speed of the device due to the rapid correction of information.

Fig „1 shows a functional diagram of the device; in fig. 2 - display unit construction.

The device contains a keyboard 1, shift register 2, parallel registers 3, block of elements AND 4, block of elements NOT 5, block 6 of indication, counter 7, element 8 of indication, -triggers 9-12, elements of AND 13-17, elements OR 18 and 19, the elements are NOT 20 and 21.

The display unit contains the element NOT 22, the decoders 23 and 24, the elements; AND-NOT 25, the elements And 26, the segment indicator 27 and the resistors 28.

The device works in the following way.

Before the device starts operating, the circuits are reset to the initial state by applying the Reset signal. As a result, the shift register 2 is in the first state, in which the first element of block 4 is prepared for operation with a signal coming from the first bit output of register 2, and the counter 7 is in the zero state, and the digit 8 is displayed on the display element 8

Then the process of entry is carried out. yes coded information in parallel ™

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Real registers 3 by alternately pressing the corresponding yupavish keyboard 1 with

When the selected key of the keyboard 1 is pressed, the normally closed contacts of this key open, which corresponds to a positive signal at the normally open contact (Clav) and. This signal, acting on the corresponding inputs of the OR elements, generates at the output of the keyboard 1 code corresponding to the key pressed. This code goes to the information inputs of the parallel registers 3 and through the elements NOT 5 to the inputs of the AND element 14

When you press each key of the keyboard 1 with the exception of the first, corresponding to coding zero, the output of the keyboard 1 generates a code different from zero, which in the inverse form is present at the inputs of the second element And 14, prohibiting its operation. When pressing the first key corresponding to zero, at the output of keyboard 1 there is a code zero, and the impulse generated when the normally closed contact of the key is opened passes through the element NOT 20 prohibits the operation of the second element 14, thereby allowing the operation of the first trigger 9 "

When the normally open contacts of the selected key of the keyboard 1 are closed, a bounce occurs, which enters the installation input of the first trigger 9. The trigger 9, by the first bounce pulse sufficient to operate, switches to the single state, forming the leading edge of the pulse at the forward output, which through the first element AND 13 enters the first inputs of the elements AND 4 blocks and through the elements OR 18 and 19 to the direct inputs of the count register 2 shift and counter 7 o Since the first element of block 4 is prepared ONLY, this imp ls is input to the first parallel synchronization register 3, recording is performed coded information from the keyboard to the outputs 1

When the selected keyboard key 1 returns to the initial state, a normally closed contact of the key occurs, followed by

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from 0 s

0

five

bounce. The bounce pulses through the HE elements 5 and the second element I 14 enter the reset input of the first trigger 9, which, by the first bounce pulse sufficient to operate, switches to the zero state, forming the falling edge of the pulse entering the forward counting inputs of the shift register 2 and counter 7, which are switched to the second position, while the shift register 2 prepares the second element 4 for operation, and element 8 and the indication block 6 of the counter 7 and the first parallel register 3 highlight the number 1, respectively, indicating the number of the register with the recorded information, and the code corresponding to the previously pressed key, in hexadecimal form.

The process of encoding information received in the second parallel register of group 3 is similar to the described cycle. At the end of the recording cycle, the display element 8 highlights the number 2 corresponding to the register number, in which information was recorded, and the display unit 6 of the second parallel register 3 highlights the hexadecimal code recorded in the second parallel register.

Thus, the 8. indication element highlights the number corresponding to the number of the parallel register 3 that was recorded in the display unit corresponding to this number of the parallel register. 3, highlighting the hexadecimal code recorded in this parallel register

Writing the coded information into parallel registers 3 continues until information is written into the last parallel register 3. On the falling edge, the pulse recording information into the last parallel register 3, the shift register 2 switches to the transfer state, prohibiting the operation of the first element 13 and 13 to form a permitting signal at the input of the fourth element AND 16 In this case, the display element 8 highlights the number corresponding to the number of the last parallel register 3 in which the recording was made, and the display unit 6, with the corresponding parallel register number 3, highlights the hexadecimal code written in the parallel register

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Thus, in parallel registers 3, information prepared for transfer to a computer is recorded, the value of which is visually displayed in display units 6. Then, the prepared information G is visually compared with a specified value, and if they are equal, it is transferred to a computer by pressing the Output key. To eliminate chatter at the time of closing and opening the contacts in the device circuit, there is a second trigger 10, which at the direct output generates an enable signal to the input of the fourth element AND 16 o. As a result, the signal of the fourth element And 16 forms the signal of the Ready device. The computer receives the information located on the informational outputs of the device, and after receiving the information, generates a Reset Pulse on the line, which returns trigger shift 2 to the first state.

By pressing the key step of the key 1 with the help of the third trigger designed to eliminate the fault at the moment of closing and opening the contacts, a pulse is generated on the falling edge of which the shift register 2 and the counter 7 switch to the next state

10 countdown

The counting process continues until the number in element 8 is less than the number of the required register number 3. Then

15 vishu Reverse of the keyboard 1 is set to the position at which the fourth trigger 12 switches to the zero state, forming on the inverse of the signal during the inversion

The 20th element And 15c, Then, the keyboard key 1 is pressed to correspond to the value of the information being encoded. As a result, the information is being rewritten.

25 in this parallel register 3 according to the described cycle. The process of adjusting the remaining parallel registers 3 is similar to that described.

After the completion of the correction process

and counter 7 is zero. As a result, 30 tirovatsii using the Step key

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By pressing the keypad key 1 with the third trigger 11, designed to eliminate chatter at the moment of closing and opening the contacts, a pulse is generated, on the falling edge of which the shift register 2 and counter 7 switch to the next state in the forward or right direction.

10 countdown

The counting process continues until the number in element 8 is 1 less than the number of the required parallel register 3. After that, the keyboard of the keyboard 1 reverse is set to the position where the fourth trigger 12 switches to the zero state, forming a signal on the inverse output allowing the operation of the third element 15s, then pressing the keyboard 1 key corresponding to the value of the information to be encoded. As a result, the process of rewriting information

25 in this parallel register 3 according to the described cycle. The process of adjusting the remaining parallel registers 3 is similar to that described.

After the completion of the correction process

this, on the display element 8, is highlighted O, which indicates that the typed information from the parallel registers 3 is transmitted to the computer

The coding and recording process of the next information is repeated.

In case of inconsistency of the typed information with the specified value, the process of correcting this parallel register 3 (tetrad) is performed as follows. First, the number of the parallel register 3 to be corrected is visually determined, and depending on the value of the digital value on the display element 8, the position of the Reverse key on the keyboard 1 is determined, with the help of which through the fourth trigger 12, designed to eliminate bounce at the moment of closing and opening the contacts , the third element AND 15 is prepared for operation, intended for organizing a direct account in the shift register 2 and the counter 7 through the first and second elements OR 18 and 19, respectively, or the fifth element And 17, designed to organize the countdown in the shift register and the counter 7, 5

0

five

0

five

keypads 1 sequentially advance 1 in shift register 2, operating in direct counting mode, until it appears at the rewrite output. Then, the information contained in the display units 6 is compared once more with the given one, and if they coincide, the Output key is pressed.

Element 8 and display unit 6 provide visual indication in hexadecimal code using jrnpaB-segments in indicator 27, based on blanking indicator segments when flashing hexadecimal digits from 9 to F. This is provided as follows. In the mode of flashing numbers from O-7, the first decoder 23 operates, forming a seven-segment code at its outputs to control the indicator 27,

When the numbers from 8 to F are highlighted, the operation of the first decoder 23 is prohibited and the second decoder 24 and the AND-NOT 25 elements are prepared for operation by a signal received at the fourth input of the display unit. NO elements. 25, by flashing the number 8, ensure ignition of all

indicator segments 27, and by flashing numbers 9 to F, the outputs of the second decoder generate signals that, passing through the corresponding AND 26 elements, prohibit the operation. certain elements of the IS-NOT 25 group, which prohibit the ignition of specific segments of the indicators 27, ensuring flashing the corresponding digit.

Thus, the device provides an indication of the typed information and its operational correction.

Claims (1)

Invention Formula A device for entering information containing a keyboard, a shift register, parallel registers, a block of elements AND, a block of elements NOT, a first trigger, two elements AND, and two elements NOT, information keyboard codes connected to information inputs of parallel registers and inputs of a block of elements NOT whose outputs connected to the inputs of the second element And, the output of which is connected to the reset input of the first trigger, the output of which is connected to the first input of the first element And, the output of which is connected to the inputs of the first group of the element in And, the outputs of which are connected to the synchronization inputs of the corresponding parallel registers, the outputs of which are informational, the outputs of the device, the information outputs of the shift register are connected to the inputs of the second group of the I block, the transfer output of the shift register is connected to the input of the second element HE, the output of which is connected to the second input of the first element And the first control output of the keyboard is connected to the input of the first element NOT, the output of which is connected to the input of the second element And, the second control output of the keyboard is connected to the installation input of the first trigger, the reset input of the shift register is a device reset input, characterized in that, in order to increase the speed of the device due to the operative correction of information, the device contains a display unit, a counter, the display element, the second, third and fourth triggers, the third, fourth and fifth elements of AND, the first and second elements of OR, the outputs of the parallel registers are connected to the inputs of the display unit, the reset input of the shift register, about By resetting the counter, the outputs of which are connected to the Inputs of the display element, the third and fourth, fifth and sixth, seventh and eighth equating keyboard outputs are connected to the installation and reset inputs of the second, third and fourth triggers, respectively. the input of the fourth element And, the output of which is the output of the readiness of the device, the second input of the fourth And with the overflow output of the shift register, the output of the third hour of the trigger with the first inputs of the third and fifth elements of I, the second inputs of which are connected respectively to the inverse and direct outputs of the fourth trigger, the output of the third element I with the first inputs of the first and second elements OR, the outputs of which are connected respectively to the input of the direct shift of the shift register and the summing input of the counter, to the second inputs of the first and second elements OR the output of the first element AND, the output of the fifth element AND connected to the input of the reverse shift of the shift register and the subtractive input of the counter.