SU693372A1 - Divider - Google Patents

Description

(54) DEVICE FOR FISSION

The invention relates to computing and can be applied to digital measuring devices. A device for dividing is known, which contains counters for the divisor, the dividend and the whole result 1. However, this device has a low accuracy, which makes it possible to determine only the whole part of the private part. The closest in technical essence to the invention is a device containing the first, second, third and fourth elements AND, the first element OR, the frequency divider, the counter of the integer part of the result, the counter of the fractional part of the result, the divisible counter, the divisor counter, the memory block , the first and second triggers, with the first input bus of the device connected to the first inputs of the first and second elements AND, the outputs of which are connected to the input of a frequency divider and the first input of the first element OR, respectively, the second input of which Connected to the output of the frequency divider, the first and second inputs of the third element 1I are connected respectively to the first output of the first trigger and the output of the divider counter, and the output of the third element I is connected to the input account; Chick is the whole part of the result, the first and second inputs of the fourth element And, respectively connected to the second output of the first trigger and the output of the divider counter, and the output of the fourth element I is connected to the fractional counter pe3yjibTaTa, the first and second input buses of the device are respectively connected to the first input of the first the second trigger of the first trigger is connected to the second input of the first element AND 2. The disadvantages of this device are the complexity and the impossibility of performing the division operation in the case when the dividend is less than the divider. The aim of the invention is to simplify and expand the field of application of the device by performing a division operation, for any divisible-divider ratio. For this, a block of AND elements, c4eTVKK residue, the second and third OR / fifth elements, AND element are introduced into the device, and the input of the residue counter is connected to the output of the first

element OR, and the output with the first input of the second element OR, the second input of which is connected to the output of the fifth element AND, the output of the second element OR is the output of the device, the output of the divisible estimator is connected to the first inputs of the fifth element AND and the second trigger , as well as with the second input of the first trigger, the outputs of the elements and the block are connected to the information inputs of the divider counter, the output of which is connected to the first group of inputs of the electronic block And, to the second input, and the first input of the third element OR, the second Bi; xcSci to torogo vhbdny connected to the second bus and the devices, and a second 1yh6d vhrdom second trigger .First vyhodkbtorzg Cpd eB vhodbm second second AND gate, and the second output - with a third input of said first and fourth members and, first; the device input bus is connected to the input of the MogO Delhi counter; , the outputs of the memory block are connected to the second group of inputs of the ele; KYuN: TovI. /;.: ;;;;. : -: ...-;.,.:, ::; The drawing shows the functional scheme of devices for divisions. :,.

The device contains: divider 1 frequency, counted 2 residuals, divisible counter 3, divisor counter 4, blinker 5 SECHtydv I, memory block b, counter 7 of the whole result, counter 8 of fractional RheulVTata, first and second triggers 9 and 10, elements AND 11-15, elements OR i6-18, first and in (tires 19 and 20 devices, you: move; 21 devices; ;; -;.; .S: Set p6Ybt E (e is in the following

; .. /;.-г---: /

yt Before the beginning of the division cycle in the counter 3, the Divisible is written down, and the counter is 2, the counter 4 and the memory block 6 are written (ect divider ;;;

It is worth noting that .2, .3, and 4 counters are ordinary binary ones that work on a computation, i.e. The transfer signal appears on their output after the arrival of the input of the indicated counters of the numbers of pulses of equal number y stored in them.

 dividing starts from the moment the pulses arrive at the bus 20 and b | rd time arrivals at the bus-19 counting pulses.

Consider the operation of the device for with three applications:

1. A divisible divider, the divisor does not fit into the divisible integer Number of times, i.e. the remainder

Dividing is not equal to zero.

2. Divisible MBHbijie divisor

3. Divisible is more divider, and Divider is placed in divisible

integer number, tv the remainder of the division is zero.

Let the dividend be A, the divisor B, and the remainder of the division. In addition, let and; K be put in with AK times, where K is an integer.

The impulse from the bus 20 enters the input of the first trigger 9 and through the element OR 18 to the input of the second trigger 10, sets them in such a way that the elements 11, 12 and. 14 are closed at the inputs i associated with these triggers, and element I 13 is the open.

Impulses arriving at input 19

5 devices are fed to the subtraction in counters 3 and 4. After entering

to the input of these counters are b pulses. at the output of the counter -4, the divider of the transfer pulse passing through the element AND 13 to the input of the counter 7, and through the element OR 18 to the input of the Trigger 10, confirms; his condition. Simultaneously / with this im-. pulse transfer from the output of the counter de. littel is fed to the input of block 5 and

5 rewrites the value of the divider from the blog 6 memory to the counter 4 of the divider. As a result, the transfer pulses at the output of the divider counter. blow every time after

0 arrival at its entrance to the pulses. After arriving at the entrance account. 3 and 4 counts of pulses

equal To ".B in the counter 3 dividend:; will remain recorded number equal to

5, moreover, .V The arrival at the input of the counters 3 and 4 of still C pulses will cause: the appearance of a pulse

sa with. output counter 3 divisible,. and in the counter 4 dividers to this KIO-.

0 cop will be recorded number

equal to BC The transfer pulse from the output of the counter 3 of the dividend will turn over / flip-flops 9 and 10, thereby breaking the passage of the input pulses

from. with SHIy 1.9 devices through elem.nt I 12 to the input of the counter 2 of the remainder and prohibit the passage of transfer pulses from the output of the counter 4. divider to the input of the counter 7. Elements 11 and 14 at 3TOMj take it to the fact that the input associated with Trigger 9, they. will appear open, will be closed on INPUT, associated with trigger 10.

Also, after flip trig

5 Hera 9, the AND 13 element will also be closed, as a result of which the passage of the pulses through the AND 13 element to the input of the counter 7 stops, and the K number equal to the whole of the division of divisible A by the divisor B appears in it. the result of the trigger trigger 10, the input pulses are fed to the input of counter 2, when 5 the number of these pulses is determined by the interval, the beginning of which coincides with the transfer pulse from the output, the divisor’s bar count, and the end with the moment of termination (K + 1) divide l that passes through the OR element 18 to the second input of the trigger 10 and returns it to its original state. This is the number of pulses in the rac. The number that will remain recorded in counter 2 of the remainder {as mentioned above, the number B) was written in it before the arrival of these pulses will be equal to B- (B – C) C - the remainder. Thus, at the specified time interval, a record in the counter 2 of the remainder of the number C occurs. In order for this period of time, the input pulses through the element 11 and transfer pulses from you, and the counter 4 divider through the element 14 do not pass to the divisor 1.And the counter 8.respectively, these elements are blocked by the gate for a given period of time from the output of the second shoulder of the trigger 10. After the end of this gate, the input pulses begin to enter the input of divider 1 through the elemen And llf achogo pulses with a frequency following time change With the frequency1 of the input pulses, the element OR 16 is fed to counter 2 residues. . The number of input pulses required to receive the transfer pulse from the output of counter 2 is determined by the number recorded in it, and it will be equal to CK. As already noted, (the K- (1) -th impulse of transfer from the output of the divider counter does not pass through the element I 14 to the input of the counter of the other terminal 3, and they will be transmitted to the given counter , as a trigger 10 (K + 1) -th transfer impulse from the counter output. The divider returns to its original state and opens the data input to E 14. The division process continues until the transfer pulse from the counter output 2 output balance an OR element 17. Since the number of input pulses needed to produce a pulse. -c, the number of transfer pulses passing to counter 8 is equal to Hl B. Thus, as a result of doing the counter 7, the number / fraction in counter 8 is fractional, the result is number k. Now consider the case when the dividend A smaller divider B. In this case, the operation of the device is similar to that previously discussed, except that the transfer 7 pulses from the output of the splitter counter will not pass through the entire recalculation cycle, since the first transfer pulse from the output of the counter 4 will occur In this case, after the appearance of the transfer pulse from the output of the counter 3 of the dividend. Due to this, all transfer pulses from the output of the counter 4 of the divider, with the exception of the first one, are recorded in the counter 8.. Indeed, the occurrence of a transfer pulse at the output of the counter 3 demo 3 stops the transfer pulses from the output of the counter 4 divider to the input of counter 7 and will allow the input pulses to pass through the element OR 16 ,, to. input counter 2 residue. The first impulse of transfer from the entry of the counter 4 divider after its 6 ending: neither prohibits the passage of-. of the INPUT pulses to the input of counter 2 of the remainder and resolves all the following transfer pulses from the output of counter 4 of the divider to the counter B. Since the number of pulses in the end of the first transfer pulse from the output of the divider counter is equal to B -BUT. Since, initially, B pulses were recorded in the residual counter, by the end of the first; transfer pulse from the counter- output. Each divider in it will turn out to be recorded B- (B-A) AA pulses. As a result, by the time a pulse appears at the output of the element OR 17 — the counter 8 will pass the AK quantity. In the transfer pulses from the output of the counter 4 is a divider. The integer count will write zero. In the event that, when dividing A by divisor B, the remainder C is zero, i.e AiKB, in this case the operation of the device is similar to the case considered by Bbime, when AGB, with the only exception that the appearance of the transfer pulse from the output of the counter 3 of the dividend and the K-th transfer pulse from the output of the counter 4 divider coincides in this case in time Due to this, an impulse appears at the output of AND 15, which, having passed through the element OR 17, indicates the end of the division process. Thus, the end of the division cycle in counter 7 will be recorded, K pulses, and in counter 8-0. Thus, the device is operational in any quantitative relationship between the fine and the divider. In addition, the device is meaning MbHQ GF & Noble. The last can be shown by determining the number of microbirds of the series 13 3 and resizing the main components of the known and proposed devices. For definiteness, it was considered that the number of digits is equal to 12, It turned out that 88 cases are required for the implementation of the known device, and 50 cases for the implementation of this device. Claims of the invention: A device for dividing, containing the first, second, third and fourth elements AND, the first element. OR Frequency divider, result integer counter, fractional hour counter, divisible counter, divisor counter, memory block, first. the second triggers, the first input to the device bus is connected to the first inputs of the first and second And elements, the first outputs of which are connected to the inputs of the frequency divider and the primary input of the first element OR, respectively, the second input of which is; Hog connected to the output of the cases; the frequency of the first and second jihbins of the third element I are connected, respectively, with the first output of the first trigger; and vyhbdom counter divider, and the output of the third element And with I: 6d6m sc% tchika of the result of the result, - the first and second inputs of the fourth element The fractional parts of the result, the second and first void devices of the device are respectively connected to the first input of the first trigger AND to the control input of the splitter counter, the second input of the first trigger is connected to the second input of the first element AND, in that in order to simplify and expand the area of the device use by performing dividing operations for any ratio of the dividend and divisor, a. The device introduced a block of elements And, the remainder counter, the second and third elements. OR, the fifth element, and the input of the counter: residue is connected to the output of the first element OR, and the output - to the first input of the second element OR, the second input of which is connected to the output of the fifth element. And, the output of the second element OR is the device output, output divisible counter connected to the first inputs of the P element And the second trigger, as well as the second input of the first trigger, outputs. H9E§ ,. And connected with information inputs of the counter divider, ° D io oporo connected with the first group of inputs of the block of elements AND, with the second input of the fifth element And. and / the first input of TpieTbero of the OR, the second input of which is connected to the second input bus of the device, and the output is with the second input of the second trigger, the first output of which is connected to the second input of the second element AND, and the second output to the third inputs of the first and fourth elements AND, the first input bus of the device connected to the input of the dividend counter us with the second group of inputs and block elements. . Sources of information taken into account during the examination 1. USSR Author's Certificate No. 392495, cl. G F 7/39, 1973. 2. USSR Copyright Certificate 512468, KL.S.06 F 7/39, 1976.,