SU1169012A1 - Indicating device - Google Patents

Abstract

1. A DISPLAY DEVICE containing a register block, a character decoder, a segment decoder, a display unit and a counter whose counting input is the first input of the device and the output is connected to the character decoder input, one of the outputs of which is connected to one of the display unit inputs the other input of which is connected to the output of the segment decoder, characterized in that, in order to increase the reliability of the device by eliminating display failures when entering information, it contains a delay element, the input of which is connected to A counter input and the output are connected to the first synchronization input of the register block, the second synchronization input of which is connected to the meter zero setting input and is the second input of the device, the third input of which is connected to the information input of the register block whose control input of the operating mode is connected to another output the decoder characters, and the output of the block of registers connected to the input of the decoder segments. 2. The device according to claim 1, characterized in that the block of registers contains n serially connected Igot2pt1-bit registers (where n is the number of characters; m is the number of segments), with the output of the n-th register connected to the input of the first register, and the first, second, and third control inputs of the second register are, respectively, the second one (L and the first synchronization inputs and the control input of the unit operation mode, the information input of each subsequent register, except the first one, is connected to the corresponding bit output of the previous register, and a quarter The first control input of the first register is the information input of the block.

Description

The invention relates to automation and computing and can be used in information output and display devices. The aim of the invention is to improve the reliability of the device due to the elimination of display failures when entering information. FIG. 1 shows a block diagram of the display device; in fig. 2 - functional block registers; in fig. 3 - timing diagrams for the operation of the device. The device for indication (Fig. 1) contains a counter 1, a decoder of 2 characters, a block 3 of indication, a decoder of 4 segments, a block of 5 registers and a delay element 6. The device blocks have inputs and outputs 7-11. Block 5 of registers (Fig. 2) contains n serially connected log mj-bits of registers 2, where n (m) is equal to the number of characters (segments) of the indication of block 3. The output of the last n-th register is connected to the inputs of the first register, the information input of the first Register 12 is the informational input 9 of register 5, the information input of each subsequent register 12 is connected to the higher-order master bit of the same register, the control inputs for the operation of all registers are combined with the control input 8 for the operation mode of register 5, first entry si chronization all registers connected to a first input 10, a synchronization unit 5 registers, a second input synchronization registers 12 connected to the second input 11, a synchronization unit 5 registers. The output of block 5 of registers is the output of the last register 12. The device operates as follows. To the counting input of the counter 1 pulses and to the input of the delay element 6 receives a fire signal 1o (Fig. 3). In the information recording mode, an information signal is also received at information input 9 of block 5 of registers in a sequential binary part code. At the same time, the first synchronization input 10 of block 5 of registers is input and the input of the installation “About counter 1” receives a clock sequence and pulses If, the number of pulses in which N is equal to the number of binary bits of the information signal N logamj-n. Moments of pulse fy coincide with moments the pulses of the reference signal fo, therefore, the counter 1 at the moment Ij is set to the zero state for the entire duration of the clock signal f. From the output of counter 1, the digital signal is fed to the decoder 2, the output 7 of the decoder 2 shows the logical signal "1, and the remaining outputs are decrypted .1 2 and 2 the signals are zero. No power is supplied to any of the indication elements of the indication unit 3 and the indication unit 3 is in the off state. A single signal from the output 7 of the decoder 2 is fed to the input 8 of the control mode of operation of the block 5 registers. The latter is set to the recording mode of the diagnostic information, with all n registers 12 of register 5 of the registers being in the shift mode, and in general the register block 5 is an N-bit shift register controlled by the clock signal Fj arriving at the first input 10 sync. At the time of the cut-off of each pulse of the signal f, one bit of the information signal 3 is recorded in the block 5 of registers, per and clock ticks fj. Signal 3 is fully written to registers 12, towards the end of the record to; Each of the registers 12 contains the code of one. of decimal digits (i (ala 3. At the end of the pulse sequence (at time tg) jio, each), the second pulse and the counter 1 changes its state. At output 7 of the decoder 2, is a logical signal "O, the register unit 5 goes into cyclic shift mode of decimal digits. In this case, each of the registers 12 goes into the parallel information recording mode, the recording process is controlled by the IMC signal M received at the second synchronization input 1 block 5 registers. Because to the second input 1 of synchronization} of the block 5. of the registers, the reference signal fo is fed through delay element 6, then each pulse of the signal fo, which appeared after the time t, with its falling edge overwrites the registers 12. In this case, the output of the block 5 of registers is successively replaced codes of characters previously written in it. Decoder 4 implises the conversion of q.ta marks into the control code of display unit 3. Counter G changes its state synchronously with register register overwriting 12. At the outputs of the decoder 2, the signal is logical 1 1 with each pulse Igna fp advances to the next exit. As a result, the indicators of the display unit 3 are sequentially switched synchronously with the change of the character codes of the signal L on the control inputs of the display unit 3. This makes it possible to fully reflect on block 3 the number recorded in block 5 of the registers. During the counting process, the counter 1 repeatedly passes the zero state. In this case, as in the information recording mode, unit 3 is turned off completely, unit 5 registers with a signal from the zero output 7 of the decoder 2 is transferred to the recording mode of sequential information, therefore the pulse of the signal fo, which brought the counter 1 to zero, with unit 5 registers no change

the output signal of block 5 does not produce registers, i.e. the transition of the counter through the zero state does not lead to a failure of the display device. A brief, for the period of the signal fo, the disconnection of the display unit 3 is not visually perceived.

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Claims (2)

1. DEVICE FOR INDICATION, comprising a register block, a character decoder, a segment decoder, an indication unit and a counter, the counting input of which is the first input of the device, and the output is connected to the input of the character decoder, one of the outputs of which is connected to one of the inputs of the display unit, the other the input of which is connected to the output of the segment decoder, characterized in that, in order to increase the reliability of the device by eliminating display failures when entering information, it contains a delay element, the input of which is connected to the counting by the counter, and the output is connected to the first synchronization input of the register block, the second synchronization input of which is connected to the counter zero input and is the second input of the device, the third input of which is connected to the information input of the register block, the operation mode control input of which is connected to the other output of the character decoder , and the output of the register block is connected to the input of the segment decoder. 2. The device according to π. 1, characterized in that the block of registers contains η sequentially connected [logs of bit registers (where η is the number of characters; m is the number of segments), and the output of the ηth register is connected to the input of the first register, and the first, second and third control inputs of each register are respectively the second and first synchronization inputs and the control unit operating mode input, the information input of each subsequent register, except for the first, is connected to the corresponding bit output of the previous register, and the fourth control input is of the register is the information input of the block. Figure 1