SU1755284A1 - Device for checking information - Google Patents

Abstract

The invention relates to automation and computing and can be used in process control systems and computer aided design systems. The aim of the invention is to increase the reliability of the control. An encoder, two comparison blocks, an OR element, three triggers, two AND elements are entered into the device, which ensures that the device does not produce incorrect control results that are distorted by randomly writing information into memory blocks. 2 Il.

Description

The invention relates to the field of automation and computer technology and can be used in process control systems.

The purpose of the invention is to increase the reliability of the control.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of a memory block.

The device contains a multiplexer 1, a group of 2 memory blocks, a counter 3, a decoder 4, a trigger 5, a clock generator 6, elements 7 and 8 AND, a multiplexer 9, a group of elements 10 OR, counters 11 and 12, a decoder 13, element 14 EXCLUSIVE OR, encoder 15, comparison blocks 16 and 17, 18, 19, 20, elements 21 and 22 AND, elements 23 OR, control information input group 24 devices, inputs 25 and 26, the device initial conditions, device synchronous input 27, task input 28 device operation modes, device address inputs 29, output 30, device control output, outputs 31 and 32 addresses of the analyzed words of the device, output 33 of the code of the number of device control cycles, outputs 34 and 35 of the display.

The device works as follows.

In the initial state, some initial information from the inputs 24 of the device is recorded in the memory blocks 2. Parallel recording of information into all bits of the corresponding memory block is carried out as follows: information is fed to the data inputs of register D1-D4, a single signal is fed to input V2, and information is written to the register by the front of the pulse at input 29 of the corresponding block 2.

The device has two basic modes of control information: mode

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sequential control and selective control mode. In these modes, a zero potential is established at the inputs of the memory blocks 2. After a general reset and start of generator b at input 28 (general reset circuits are not shown), through element I 7, the inputs of the decoder 4 and 13 receive pulses from generator 6j which appear at the outputs of the decoder corresponding to the codes contained respectively in counters 3 and 11. These signals are used in memory units 2 as shear. The address signals from the outputs of counters 3 and 11 are also sent to multiplexers 1 and 9, and from their outputs, a bit of information from the outputs of the corresponding memory blocks is switched; at the output of the EXCLUSIVE OR 14 element, in the case of a discrepancy between the values of the individual bits of the compared data words, single pulses appear for the duration of the clock period. At the same time, information from the output of memory 2 is written to its lower order, providing non-destructive readout and formations from the memory,

In sequential control mode, a pairwise comparison of the contents of all memory blocks is performed. After a general reset of the device, counters 3, 11, 12, triggers 18, 19, and 20 are cleared, and trigger 5 is in one state. The trigger 5 allows after starting the device the passage of a single pulse from the generator through the element And 8 to the reset input of the trigger 5 and to the counting input of the counter 11, incrementing its contents. Thus, content O and 1, respectively, of counters 3 and 11 is provided. This content defines the addresses of the information words in the first pair of compared memory blocks 2.

When the triter 5 goes to the zero state, the And 8 element closes and the And 7 element opens, allowing the following pulses to pass from the generator to the inputs of the decoder 4 and 13. The comparison of two words in memory blocks 2 begins. Through K + 1 pulse (where K - word width in memory blocks 2) counter 12 is zeroed out and an overflow signal is given, which is fed to the input of setting trigger unit 5. Element And 8 passes one pulse again, increments counter 11 and re-sets trigger 5 to zero condition A comparison of the next couple of words,

Thus, the memory blocks 2 involved in the comparison are performed by counters 3 and 11. Initially, these counters are respectively in O and 1 states, after the first overflow pulse from counter 12, in O and 2 and so on. d., until the states O and nG are reached. Then, from the overflow output of counter 11, a signal is received that increments the contents of counter 3 and starts a new comparison cycle — from O, and so on — to from n-1. This continues until all pairs of blocks are compared.

0 memory 2. At the same time, outputs 31 and 32 at any time contain addresses of the words being compared, output 33 is the cycle number (bit number) of the word pair being compared, and at control output 30 is a single signal in the event of a mismatch of the corresponding word yes comparable words

In the selective control mode of the counter 3 and 11, the control signal to the input 27 is switched to the mode

0 parallel entries, and they write the required addresses to the inputs, respectively, 25 and 26, Next, the comparison process is performed as described.

It is also possible to output some information from the device unchanged, without comparison. To do this, it is necessary to write down the zero word in one of the memory blocks and, in the selective control mode, to perform the control of the required word, comparing it with

0 zero.

The device also provides the recording of new information in an arbitrary memory block at the required points in time. If the recording of information in a block of memory 5 is made at the time when this block is not involved in bitwise comparison, the distortion of the control results does not occur in principle. If the recording is made to a memory block participating in

At this time point in comparison, the elimination of distortions of the control results in the device is carried out as follows.

Write new information to some

5, the memory block 2 is produced by installing a new word on the inputs D1-D4 / Dk with the K-bit words of the suburban block indicated. In this case, the signal from the device input 29 also goes to the corresponding input

0 encoder 15. converts the position code at the inputs to the output binary code. This binary code is the address of memory block 2, in which information is currently being written. This comparison is compared in the blocks of comparison 16 and 17 with the addresses of the blocks participating in the control at the moment of recording and formed respectively by the counters 3 and 11. If it does not coincide with one of the two addresses, information distortion (results) will occur

It cannot, and in this situation, the operation of the device does not differ from that described. If the address from the output of the encoder 15 coincides with one of the addresses in counter 3 or 11, the results of the control of this pair of words will be incorrect, since as a result of writing new information, the comparison of this pair will be partially made with the old word, and partially with the new one. At the same time, a positive signal appears from the output Equal to the corresponding comparison block 16 or 17, which sets the triggers 19 and 20, respectively, to indicate that this comparison step contains an incorrect result, and, moreover, specifying which memory block ti changed content as a result of recording new information.

At the same time, the signal Equals through the element IL AND 23 to the input of the installation of the trigger 18, which closes the element AND 22 and opens the element / 21. At the same time, the overflow signal generated from the output of the counter 12 resets the trigger 18, but is not set And the trigger 5, prohibiting the impending of counter 11. Thus, the monitoring step in which an incorrect result was obtained due to the recording of new information and one of the memory blocks is repeated.

The device allows to realize sequential and selective operation modes of control information and direct output mode. At the same time, the device prevents the user from receiving incorrect control results, distorted by randomly writing information into memory blocks, which, in turn, ensures the absence of information aging processes due to the timely recording of new data with virtually no delay in the corresponding memory blocks.

Control violation signals are maintained until the user is given the result (correct) comparison of the contents of this pair of memory blocks; these signals are taken at the same time as the trigger 5 is set to one.

Claims (1)

Claims An information control device comprising two decoders, an OR group, a group of memory blocks, two multiplexers, three counters, two AND elements, a clock generator, an EXCLUSIVE OR element, the first trigger, and the groups of bit outputs of the first and second counters connected respectively to the groups of address inputs of the first and second multiplexers and groups of information inputs of the first and second decoders, group of inputs of the monitored information of the device are connected respectively groups of information inputs of the corresponding memory blocks, the synchronization inputs of which are connected respectively to the outputs of the corresponding elements OR groups, the first and second inputs of which are connected to the outputs of the first and second decoders, the gate inputs of which are connected to the output of the first And element, the recording control inputs of memory blocks These groups are connected to the group of address inputs by a device record, the output of the 1st block of the group of memory blocks (where i 1-n, n is the number of words in the monitored information) is connected to the information of the same name The primary inputs of the first and second multiplexers, the outputs of which are connected to the first and second inputs of the EXCLUSIVE OR element, whose output is the control output of the device, the synchronous input of the device connected to the synchronous input of the first and second counters, the summing input of the first counter connected to the overflow output of the second counter, the job input the operating mode of the device is connected to the start input of a clock generator, the output of which is connected to the counting input of the third counter, with the first inputs of the first and volts And, the bit outputs of the third counter are outputs of the code number of device control cycles, the output of the second element AND is connected to the summing input of the second counter and the reset input of the first trigger, the forward and inverse outputs of which are connected respectively to the second inputs of the second and first elements And, the groups of information inputs of the first and second counters are the first and second groups of inputs for setting the initial conditions, the device, characterized in that, in order to increase the reliability of the control, an encoder, two comparison blocks, an OR element, three triggers, two AND elements are entered, the device’s address input group is connected to the encoder’s information input group, the output group of which is connected to the first input groups of the first and second comparison blocks, the second input groups of which are connected respectively to groups of outputs of the first and second counters, which are respectively outputs of the address of the first and second analyzed words of the device, outputs Equal to the first and second Comparison units are connected respectively to the first and second inputs of the OR element and to the installation inputs of the second and third triggers, the forward outputs of which are outputs of the indication of the correctness of checking device data, the output of the OR element is connected to the installation input of the fourth trigger, the forward and inverse outputs of which connected according 24 Downstairs with the first inputs of the third and fourth elements And, the output of the third element I is connected to the reset input of the fourth trigger, the output of the fourth element I is connected to the reset inputs of the second and third triggers and the installation input of the first trigger, the overflow output of the third counter is connected to the second inputs of the third and fourth elements I. M Ј-4- & about $ 29 Otnlvl, ft4