SU1332365A1 - Indicating device - Google Patents

Abstract

The invention relates to computing and can be used in digital devices requiring indication of the status of nodes. The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that a display device containing inputs 1, a cervical switch 2, a control I. input 3, registers 4, second switch 5, shift register 6, keys 7 and display elements 8, further comprises a pulse generator 9, a control unit 10, elements 11 and 11 and 12. The output of the pulse generator is connected to the input of the control unit, the code of which is connected with the input of the element NOT, the output of which is connected to the control input of the first switch and with one input of the element AND, the other input of which is connected to the output of the pulse generator and the input of the strobe. the first switch, and the output is from the shift register input control. This eliminates the need for manual manipulations when calling the displayed portion of information on display elements, as well as realizing the display of the displayed information in real time. 2 з.п, ф-л, 5 Il. (L from 00 Yu with Od sd

Description

The invention relates to computing and can be used in digital devices requiring indication of the status of nodes.

The purpose of the invention is to increase the speed of the device.

Fig, 1 shows a functional diagram of the device; in fig. 2 is a diagram of the first shift switch; rta 10 of FIG. 3 is a diagram of the second switch; Fig. 4 is a control block diagram; Fig. 5 shows time diagrams of the device operation.

The device contains 15 information inputs 1, the first switch 2, the control inputs 3, the shift registers 4, the second switch 5, the shift register 6, keys 7, the elements 8 of the display.

4 leads to a shift of information by one bit in the right.

The second switch (Fig. 3) is made using multiplexers 16. The control inputs of the second switch 5 receive a binary number equal to the input number of the switch 5, the signal KOTCfporo goes to the switch output.

The shift register 6 differs from the shift register 4 of the first switch 2 in that it does not have a parallel reception mode.

The control unit 10 generates a control signal having a period equal to q cycles (the time intervals between the same fronts of adjacent pulses at the output of the generator 9 and the generator of 9 pulses, block 10 of the control pulses). Managing Period

laziness, elements 11 and 11, the first switch 2 contains n-bit shift registers 4, the inputs of the parallel reception of each of which the signal consists of two sections: a section equal to n cycles, during which the control signal is zero, and plot equal to m cycles in

with the corresponding group of inputs 25 for which the control signal 1 to be displayed and the output with

is equal to one

corresponding to the discharge of the outputs of the first switch 2.

The shift register 4 (Fig. 2) contains information input 13, D-flip-flops 14, which are received by a pulse applied to the register setup input 4. Inputs D of all flip-flops 14, except the first, are connected to the outputs of multiplexers 15, the control inputs A of which are connected to the control input of the shift register 4, the inputs 1 of the multiplexer 15 are connected to the inputs of the shift register 4, and the transfer input of the multiplexer 15 is connected to the output of the corresponding trigger 14, the shift register operates in two modes determined by the input state yes control If, at the control input, the signal is equal to one (parallel reception mode), then the information from the inputs of the shift register 4 through multiplexers 15 is fed to the inputs of D-flip-flops 14 and is received into them when the pulse arrives. If the input of the shift register 4 has a signal equal to zero (shift mode), then the input of the D-trigger 14 receives a signal through multiplexer 15 from the output of the previous trigger 14. Thus, the arrival of the pulse at the input of the shift of the shift register

4 leads to a shift of information by one bit in the right.

The second switch (Fig. 3) is made using multiplexers 16. The control inputs of the second switch 5 receive a binary number equal to the input number of the switch 5, the signal KOTCfporo goes to the switch output.

The shift register 6 differs from the shift register 4 of the first switch 2 in that it does not have a parallel reception mode.

The control unit 10 generates a control signal having a period equal to q cycles (the time intervals between the same fronts of adjacent pulses at the output of the generator 9 of the tax signal consists of two sections: a section equal to n cycles, during which the control signal is zero, and equal to m cycles, in

during which control

is equal to one

q p +

sh,

0

0

where n is the width of the shift registers 4 and 6,

The quantities q and m must be chosen so that the inequality holds

m p. five

The control unit 10 (Fig. 4) contains a binary K-bit counter 17. A sequence of clock pulses arrives at the gate gate input. Each clock pulse increases the binary number contained in the counter by one.

The device works as follows.

The pulse generator 9 generates clock pulses (diagram 1, fig. 5). The control unit 10 generates a control signal (diagram 2, fig. 5), which from the output of the control unit 10 is fed to the control inputs of the shift registers 4. Thus, the shift registers 4 during m clocks / set, lena to parallel reception mode and in each clock of this mode c receive information to be displayed from inputs 1. During the subsequent n cycles the shift registers 4 are set to the shift mode. Since the shift mode continues for

five

0

n cycles, equal to the width of the shift register, the contents of each shift register 4 during this period are received sequentially from the output of the shift register 4 to the corresponding input of the second switch 5.

If necessary, indicate that

or another group of information produced

manipulations on the control panel leading to the supply to the control inputs of the device of the corresponding signal. Thus, the second switch 5 provides information to the information input of the shift register 6 of information, for n cycles

by the operator.

,

A sequence of clock pulses is supplied to the inputs of the And 12 element (diagram 1, fig. 5) and a signal from the output, the element 14 stroke (diagram 3, fig. 5). The logical product of these two signals (Diagram 4, Fig. 5) from the output of the And 12 element is fed to the control input of the shift register 6. Thus, during peaks in the shift registers 4 and 6, n information shifts are performed, which through the switch 5 is overwritten from register 4 to register 6. During the m cycles, when the shift registers 4 receive the information to be displayed in parallel, the information is not written to the shift register 6.

Information from the outputs of the shift register 6 is fed to the first inputs of the keys 7, to the second inputs of which the control signal is output from the control unit 10 (diagram 2, Fig. 5). Thus, the information contained in the shift register 6 enters the inputs of the indication elements 8 only for m cycles, and during the periods when the information in the shift register 6 is shifted, the indication elements 8 are not illuminated. Thus, information previously received in shift register 4 is displayed on display elements 8 within m TaKfoB. .

The choice of the values of the power source depends on the generator frequency of 9 clock pulses and the type of display elements 8. Greats

five

0 5 o

five

0 5

by m must exceed the size of the group n.

The device allows the computer operator to detect changes in the displayed information without additional manipulations on the control panel, and can be used in cases where the time intervals between changes of information are at least several times longer than the period of operation of the device.

Claims (3)

1. A display device comprising a first switch, the inputs of which are the information inputs of the device, the outputs of the first switch are connected to the information inputs of the second switch, the control input of which is the control input of the device, and the output connected to the information input of the shift register, information inputs which are connected to the first inputs 1 and keys whose outputs are connected to display elements, characterized in that, in order to improve the speed of the device, it contains a generator p pulses, control unit, NOT element, AND element, the output of which is connected to the gate input of the shift register, and the first input - with the output of the pulse generator connected to the gate input of the first switch and input of the control unit, the output of which is connected to the second key inputs, input element and the control input of the first switch. 2. The device according to claim 1, which is duplicated in that the first switchboard contains shift registers, the parallel receive inputs, gating and settings of which are respectively the inputs, the gate input and the control input of the first switch, the register outputs are the inputs of the first switch ... 3. Device POP.1, characterized in that the control unit contains a counter and an element WI, the inputs of which are connected to the outputs of the counter, the gating input of which is input to the control unit, the output of the OR element is the output of the control. FIG. 2 3 Editor V. Petrash Compiled by A. Mescherkov Tehred M. Didyk Corrector. Cherni Order 3837/47 Circulation 433 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, st. Project, 4 Figm